User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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20.2. DISP_SLC—Display Scan Line Count Range Compare
Memory Offset Address: 70004h
Default: 0000h
Attributes: Read only
The Top and Bottom Line Count Compare registers are compared with the display line values from
CRTTG (the CRT timing generator) or the TV/FP timing generator, depending upon whether the TV/FP
timing generator is enabled and not in FP VESA VGA Mode (LCDTV_C[31]=1 AND
LCDTV_C[28]=0) or not. The line counter changes at the leading edge of HSYNC. It can be safely read
during the display enable active time. The Top compare register operator is a less than or equal, while the
Bottom compare register operator is a greater than or equal. The results of these two comparisons are
communicated to the command stream controller for generating interrupts, status, and command stream
flow control (wait for scanline). These registers can be loaded from the command stream and read
through the PCI.
When in TV/FP centering mode, scan line 0 is the first active scan line of the TV/FP, not the first line of
the centered active display.
31 30 28 27 16
In/Ex Reserved Top Line Count Compare for Display SLC [11:00]
15 12 11 0
Reserved Bottom Line Count Compare for Display SLC [11:00]
Bit Descriptions
31 Inclusive / Exclusive.
1 = Inclusive: within the range.
0 = Exclusive: outside of the range.
30:28 Reserved.
27:16 Top Line Count Compare for Display SLC [11:00]. This register is used as the top comparison (less
than or equal to) value with the display vertical line counter.
15:12 Reserved.
11:0 Bottom Line Count Compare for Display SLC [11:00]. This register is used as the bottom
comparison (greater than or equal to) value with the display vertical line counter.