User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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20.3. Pixel Pipeline Control
20.3.1. PIXCONF—Pixel Pipeline Configuration
Memory Offset Address: 70008h
Default: 00000000h
Attributes: Read/Write
31 28 27 26 25 24
Reserved (0000) Display
Gamma
Enable
Overlay
Gamma
Enable
Reserved Reserved
23 21 20 19 16
Reserved (000) CRT
Control
Display Color Mode
15 14 13 12 11 10 9 8
8-Bit DAC
Enable
Reserved Cursor
Display
Enable
Extended
Status
Read
CRT
Overscan
Color
Reserved Palette
Addr
7 5 4 3 2 1 0
Reserved (000) Reserved
(0)
Reserved
(System
Write 32)
Reserved
(0)
VGA Wrap GUI Mode
Bit Descriptions
31:28 Reserved (0000).
27 Display path (Graphics) Gamma Enable. (See note.)
0 = 16 and 24 BPP graphics data bypasses palette (default).
1 = 16 and 24 BPP graphics data goes through palette.
26 Overlay path Gamma Enable. (See note.)
0 = Video data bypasses palette (default).
1 = Video data goes through the palette. Useful when Alpha Blending the Overlay with the Primary
Display to provide gamma correction for the display device. The Overlay Gamma Correction
should be set up to un-gamma the overlay surface bringing it into the linear space before
performing the alpha blending. Both the primary display (27 = 1) and the Overlay (26=1) should
be passed through the palette after alpha blending to provide proper gamma correction for the
display device.
25:21 Reserved (00000).
20 CRT Control Signal Delay. This bit affects CRT Display enable and CRT Blank signal delay with
respect to CRT HSYNC and CRT VSYNC when the standard VGA pixel pipeline is used by CRT
display engine. This bit has no effect on Flat Panel centering or optimized timing modes.
0 = CRT Display Enable and CRT Blank are delayed for standard VGA compatibility (default).
1 = CRT Display Enable and CRT Blank are not delayed.