User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
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20.3.5. DPLYSTAS—Display Status Select Register
Memory Offset Address: 70024h
Default: 0000h
Attributes: Read/Write
This register selects the proper events to be signaled to the Interrupt Control Register in the command
stream. Status bits 0 and 1 are logically ORed to become the Vertical Blank status bit and status bits 8, 9,
and 10 are logically ORed to become the Display Event status bit. These 2 sets of status bits are on
separate bytes for future expansion purposes. The architecture allows each byte to be logically ORed.
The enables, for each status bit is in the corresponding bit or the upper word. If a status enable bit is
asserted, then the corresponding status bit is considered in the interrupt generation. The Status bits
capture the event if enabled and are cleared by writing a 1 to the bit. This register has separate byte
enables for writing.
31 27 26 25 24
Reserved FP Hot
Plug
Enable
VSYNC
En
Vert Line
Comp En
23 18 17 16
Reserved Verit Blank
En
OVL Reg
Upd En
15 14 11 10 9 8
FP Hot
Plug Status
Reserved FP Hot
Plug
Interrupt
VSYNC Vert Line
Comp
7 2 1 0
Reserved Verit Blnk
Dply Event
Sel
OVL Reg
Upd Vblnk
Sel
Bit Descriptions
31:27 Reserved.
26 Flat Panel Hot Plug Detect Enable.
0 = Flat Panel Hot Plug Detect Disabled
1 = Flat Panel Hot Plug Detect Enabled
25 Vertical Sync Status Enable.
0 = Vertical Sync Status Disabled
1 = Vertical Sync Status Enabled
24 Display Line Compare Enable.
0 = Display Line Compare Status Disabled
1 = Display Line Compare Status Enabled