User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

Table 2. Memory-Mapped Registers

Address Offset Symbol Register Name Access

LCD/TV-Out Registers (60000h–6FFFFh)

LCD/TV-Out

60000h–60003h HTOTAL Horizontal Total R/W

60004h–60007h HBLANK Horizontal Blank R/W

60008h–6000Bh HSYNC Horizontal Sync R/W

6000Ch–6000Fh VTOTAL Vertical Total R/W

60010h–60013h VBLANK Vertical Blank R/W

60014h–60017h VSYNC Vertical Sync R/W

60018h–6001Bh LCDTV_C LCD / TV-Out Control R/W

6001Ch–6001Fh OVRACT Overlay Active Register R/W

60020h–60023h BCLRPAT Border Color Pattern R/W

60024h−6FFFFh  Reserved 

Display and Cursor Control Registers (70000h–7FFFFh)

70000h–70003h DISP_SL Display Scan Line Count R/W

70004h–70007h DISP_SLC Display Scan Line Count Range Compare R/W

70008h–7000Bh PIXCONF Pixel Pipeline Configuration R/W

7000Ch–7000Fh BLTCNTL BLT Control R/W

70010h–70013h DIAG Diagnostic R/W

70014h–7001Fh SWF[1:3] Software Flags [1:3] (3 registers) R/W

70020h–70023h DPLYBASE Display Base Address R/W

70024h–70027h DPLYSTAS Display Status Select R/W

70080h–70083h CURCNTR Cursor Control and Vertical Extension R/W

70084h–70087h CURBASE Cursor Base Address R/W

70028h–7002Bh CURPOS Cursor Position R/W

7002Ch–7FFFFh  Reserved 

3.3. VGA and Extended VGA Register Map

For I/O locations, the value in the address column represents the register I/O address. For memory

mapped locations, this address is an offset from the base address programmed in the MMADR register

(PCI Configuration register).