User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
360
Bit Descriptions
23:18 Reserved.
17 Vertical Blank Enable.
0 = Vertical Blank Status Disabled
1 = Vertical Blank Status Enabled
16 Overlay Registers Upated Enable.
0 = Overlay Registers have been updated during Vertical Blank Status Disabled
1 = Overlay Registers have been updated during Vertical Blank Status Enabled
15 Flat Panel Hot Plug Detect Status. This bit is the state of the TVCLKIN pin of the TV/Flat Panel
interface. This pin signals an interrupt when it is low. When an interrupt is asserted on the pin, this
status bit reads back as a 1. This bit is forced low when the TVCLKIN pin is selected as a Clock Input
reference to the Dot Clock PLL and NOT an Interrupt pin.
0 = Flat Panel Hot Plug Detect asserted
1 = Flat Panel Hot Plug Detect not asserted (forced to 1 when used as CLKIN)
14:11 Reserved.
10 Flat Panel Hot Plug Detect (edge catcher). This bit is the edge detector for bit 15 above. It is set to 1
when it detects a low to high transition.
0 = Flat Panel Hot Plug Detect not asserted; bit 15 has not transitioned from 1 to 0 (forced to 0 when
used as CLKIN)
1 = Flat Panel Hot Plug Detect asserted; bit 15 has transitioned from 1 to 0.
9 Vertical Sync Status.
0 = Vertical Sync not asserted
1 = Vertical Sync asserted
8 Display Line Compare Status.
0 = Display Line Compare Status not asserted
1 = Display Line Compare Status asserted
7:2 Reserved.
1 Vertical Blank Status.
0 = Vertical Blank Status not asserted
1 = Vertical Blank Status asserted
0 Overlay Registers Updated Status.
0 = Overlay Registers have been updated during Vertical Blank Status not asserted
1 = Overlay Registers have been updated during Vertical Blank Status asserted