User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
72
7.3. Display, I/O, GPIO, Clock, LCD, and Pixel Pipeline
Registers
These registers are described elsewhere in this document. Refer to the appropriate sections of this PRM
for detailed bit/field descriptions.
Address Offset Symbol Register Name Access
Instruction and Interrupt Control Registers
020D8h–020DBh FW_BLC FIFO Watermark and Burst Length Control R/W
I/O Control Registers
05000h−05003h HVSYNC HSYNC/VSYNC Control R/W
05010h−05013h GPIOA General Purpose I/O Control A R/W
05014h−05017h GPIOB General Purpose I/O Control B R/W
Clock Control and Power Management Registers
06000h−06003h DCLK_0D Display Clock 0 Divisor R/W
06004h−06007h DCLK_1D Display Clock 1 Divisor R/W
06008h−0600Bh DCLK_2D Display Clock 2 Divisor R/W
0600Ch−0600Fh LCD_CLKD LCD Clock Divisor R/W
06010h−06013h DCLK_0DS Display and LCD Clock Divisor Select R/W
06014h−06017h PWR_CLKC Power Management and Miscellaneous Clock
Control
R/W
LCD/TV-Out
60000h–60003h HTOTAL Horizontal Total R/W
60004h–60007h HBLANK Horizontal Blank R/W
60008h–6000Bh HSYNC Horizontal Sync R/W
6000Ch–6000Fh VTOTAL Vertical Total R/W
60010h–60013h VBLANK Vertical Blank R/W
60014h–60017h VSYNC Vertical Sync R/W
60018h–6001Bh LCDTV_C LCD / TV-Out Control R/W
6001Ch–6001Fh OVRACT Overlay Active Register R/W
60020h–60023h BCLRPAT Border Color Pattern R/W
Display and Cursor Control Registers
70008h–7000Bh PIXCONF Pixel Pipeline Configuration R/W