User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

Table 8. CRT Display Sync Polarities

V H Display Horizontal

Frequency

Vertical Frequency

P P >480 Line Variable Variable

P P 200 Line 15.7 KHz 60 Hz

N P 350 Line 21.8 KHz 60 Hz

P N 400 Line 31.5 KHz 70 Hz

N N 480 Line 31.5 KHz 60 Hz

9.2. Sequencer Registers

The sequencer registers are accessed via either I/O space or Memory space. To access the registers the

VGA Sequencer Index register (SRX) at I/O address 3C4h (or memory address 3C4h) is written with the

index of the desired register. Then the desired register is accessed through the data port for the sequencer

registers at I/O address 3C5 (or memory address 3C5).

9.2.1. SRX



Sequencer Index

I/O (and Memory Offset) Address: 3C4h

Default: 00h

Attributes: Read/Write

7 3 2 0

Reserved (00000) Sequencer Index

Bit Descriptions

7:3 Reserved. Read as 0s.

2:0 Sequencer Index. This field contains a 3-bit Sequencer Index value used to access sequencer data re-

gisters at indices 0 through 7.

Notes:

1. SR02 is referred to in the VGA standard as the Map Mask Register. However, the word “map” is used

with multiple meanings in the VGA standard and was, therefore, deemed too confusing; hence, the

reason for calling it the Plane Mask Register.

2. SR07 is a standard VGA register that was not documented by IBM. It is not an graphics controller

extension.