User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
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Table 9. VGA Address Range
GR10
[2]
GR10
[1]
GR10
[0]
Note 1 Address Range (see note 2)
A0000-AFFFF Range
(No GTT)
B0, B8 Ranges (No GTT)
0 0 0 Std VGA
xlations
VGA Controller, No
Paging
VGA Controller, No
Paging
0 0 1 Paging and VGA
xlation not
supported
NA NA
0 1 0 No Paging, No
VGA xlations
Bypass VGA, No Paging Bypass VGA, No Paging
0 1 1 Paging, No VGA
xlations
Bypass VGA, Paged by
GR11
Bypass VGA, No Paging
1 0 0 No Paging, No
VGA xlations
Bypass VGA, No Paging Bypass VGA, No Paging
1 0 1 Paging, No VGA
xlations
Bypass VGA, Paged by
GR11
Bypass VGA, No Paging
1 1 0 No Paging, No
VGA xlations
Bypass VGA, No Paging Bypass VGA, No Paging
1 1 1 Paging, No VGA
xlations
Bypass VGA Paged by
GR11
Bypass VGA, No Paging
NOTES:
1. GR10[2:0] must not be programmed to “001” value because the GMCH hardware does not support the paging
and VGA translation mode. Unpredictable hardware behavior will occur if GR10[2:0] were programmed to “001”
value.
2. VGA Address Range, selected by GR06, Graphics range selected through Graphics base address register in
configuration space. Access to VGA range does not require a translation table and VGA range paging allows
access to all of local memory if it is setup with bit 4 of this register or to all the stolen for VGA main memory
space. Access to graphics range requires GTT to be set up and will result in a prefetch unless prefetch is
disabled. Access to VGA range will not result in prefetch.
3. BIOS should access local memory through the "back door" mechanism by setting GR10=17h, GR11=0, and
GR6=0 only when local memory has been enabled (MMADR+3000h), else the system will hang in a snoop stall
forever.
9.3.12. GR11

Page Selector
I/O (and Memory Offset) Address: 3CFh (Index=11h)
Default : 00h
Attributes: R/W
Bit Description
7:0 Page Select. Selects a 64KB window within VGA space in NLVM mode or all of local memory when
Page Mapping is enabled (GR10[0]=1). In addition, this register is used for page selection of memory
mapped register addresses.