Specifications

x Software Developer’s Manual
Contents
12 Dual Port Characteristics....................................................................................207
12.1 Introduction .......................................................................................................207
12.2 Features of Each MAC......................................................................................207
12.2.1 PCI/PCI-X interface..........................................................................207
12.2.2 MAC Configuration Register Space .................................................209
12.2.3 SDP, LED, INT# output ....................................................................209
12.3 Shared EEPROM..............................................................................................210
12.3.1 EEPROM Map..................................................................................210
12.3.2 EEPROM Arbitration ........................................................................210
12.4 Shared FLASH..................................................................................................211
12.4.1 FLASH Access Contention...............................................................211
12.5 LAN Disable ......................................................................................................212
12.5.1 Overview ..........................................................................................212
12.5.2 Values Sampled on Reset................................................................212
12.5.3 Multi-Function Advertisement...........................................................213
12.5.4 Interrupt Use.....................................................................................213
12.5.5 Power Reporting...............................................................................213
12.5.6 Summary..........................................................................................214
13 Register Descriptions...........................................................................................215
13.1 Introduction .......................................................................................................215
13.2 Register Conventions........................................................................................215
13.2.1 Memory and I/O Address Decoding .................................................216
13.2.2 I/O-Mapped Internal Register, Internal Memory, and Flash .............217
13.3 PCI-X Register Access Split..............................................................................223
13.4 Main Register Descriptions ...............................................................................224
13.4.1 Device Control Register ...................................................................224
13.4.2 Device Status Register.....................................................................229
13.4.3 EEPROM/Flash Control & Data Register.........................................232
13.4.4 EEPROM Read Register..................................................................234
13.4.5 Flash Access....................................................................................236
13.4.6 Extended Device Control Register ...................................................237
13.4.7 MDI Control Register........................................................................242
13.4.8 Flow Control Address Low ...............................................................283
13.4.9 Flow Control Address High...............................................................283
13.4.10 Flow Control Type ............................................................................284
13.4.11 VLAN Ether Type .............................................................................284
13.4.12 Flow Control Transmit Timer Value..................................................285
13.4.13 Transmit Configuration Word Register.............................................286
13.4.14 Receive Configuration Word Register..............................................287
13.4.15 LED Control......................................................................................289
13.4.16 Packet Buffer Allocation ...................................................................292
13.4.17 Interrupt Cause Read Register.........................................................293
13.4.18 Interrupt Throttling Register..............................................................295
13.4.19 Interrupt Cause Set Register............................................................296
13.4.20 Interrupt Mask Set/Read Register....................................................297
13.4.21 Interrupt Mask Clear Register ..........................................................298
13.4.22 Receive Control Register .................................................................300
13.4.23 Flow Control Receive Threshold Low...............................................304
13.4.24 Flow Control Receive Threshold High..............................................305