Specifications

viii Software Developer’s Manual
Contents
6 Power Management...............................................................................................131
6.1 Introduction to Power Management ..................................................................131
6.2 Assumptions......................................................................................................131
6.3 D3cold support..................................................................................................132
6.3.1 Power States....................................................................................132
6.3.2 Timing...............................................................................................134
6.3.3 PCI Power Management Registers..................................................139
6.4 Wakeup.............................................................................................................143
6.4.1 Advanced Power Management Wakeup..........................................143
6.4.2 ACPI Power Management Wakeup..................................................144
6.4.3 Wakeup Packets ..............................................................................145
8 Ethernet Interface ..................................................................................................155
8.1 Introduction .......................................................................................................155
8.2 Link Interfaces Overview...................................................................................155
8.2.1 Internal SerDes Interface/TBI Mode– 1Gb/s ....................................156
8.2.2 GMII – 1 Gb/s...................................................................................157
8.2.3 MII – 10/100 Mb/s.............................................................................158
8.3 Internal Interface ...............................................................................................158
8.4 Duplex Operation ..............................................................................................158
8.4.1 Full Duplex .......................................................................................159
8.4.2 Half Duplex.......................................................................................159
8.5 Auto-Negotiation and Link Setup ......................................................................161
8.6 Auto-Negotiation and Link Setup ......................................................................161
8.6.1 Link Configuration in Internal Serdes/TBI Mode...............................162
8.6.2 Internal GMII/MII Mode.....................................................................165
8.6.3 Internal SerDes Mode Control Bit Resolution...................................168
8.6.4 Internal PHY Mode Control Bit Resolution .......................................169
8.6.5 Loss of Signal/Link Status Indication................................................171
8.7 10/100 Mb/s Specific Performance Enhancements ..........................................172
8.7.1 Adaptive IFS.....................................................................................172
8.7.2 Flow Control .....................................................................................173
8.7.3 MAC Control Frames & Reception of Flow Control Packets............173
8.7.4 Discard PAUSE Frames and Pass MAC Control Frames................175
8.7.5 Transmission of PAUSE Frames......................................................176
8.7.6 Software Initiated PAUSE Frame Transmission...............................176
8.7.7 External Control of Flow Control Operation......................................176
9 802.1q VLAN Support...........................................................................................179
9.1 802.1q VLAN Packet Format ............................................................................179
9.1.1 802.1q Tagged Frames....................................................................179
9.2 Transmitting and Receiving 802.1q Packets.....................................................180
9.2.1 Adding 802.1q Tags on Transmits ...................................................180
9.2.2 Stripping 802.1q Tags on Receives .................................................180
9.3 802.1q VLAN Packet Filtering...........................................................................180
10 Configurable LED Outputs.................................................................................183
10.1 Configurable LED Outputs ................................................................................183
10.1.1 Selecting an LED Output Source .....................................................183
10.1.2 Polarity Inversion..............................................................................184