Datasheet

Datasheet, Volume 2 179
Processor Configuration Registers
2.10.23 INTRPIN—Interrupt Pin Register
This register specifies which interrupt pin this device uses.
2.10.24 BCTRL—Bridge Control Register
This register provides extensions to the PCICMD register that are specific to PCI-PCI
bridges. The BCTRL provides additional control for the secondary interface (that is, PCI
Express-G) as well as some bits that affect the overall behavior of the "virtual" Host-
PCI Express bridge embedded within the processor; such as VGA compatible address
ranges mapping.
B/D/F/Type: 0/6/0/PCI
Address Offset: 3Dh
Reset Value: 01h
Access: RW-O, RO
Size: 8 bits
Bit Access
Reset
Value
RST/
PWR
Description
7:3 RO 00h Uncore Reserved (RSVD)
2:0 RW-O 1h Uncore
Interrupt Pin (INTPIN)
As a multifunction device, the PCI Express device may specify
any INTx (x=A,B,C,D) as its interrupt pin.
The Interrupt Pin register tells which interrupt pin the device (or
device function) uses.
A value of 1 corresponds to INTA# (Default)
A value of 2 corresponds to INTB#
A value of 3 corresponds to INTC#
A value of 4 corresponds to INTD#
Devices (or device functions) that do not use an interrupt pin
must put a 0 in this register.
The values 05h through FFh are reserved.
This register is write once. BIOS must set this register to select
the INTx to be used by this root port.
B/D/F/Type: 0/6/0/PCI
Address Offset: 3E–3Fh
Reset Value: 0000h
Access: RO, RW
Size: 16 bits
BIOS Optimal Default 0h
Bit Access
Reset
Value
RST/
PWR
Description
15:12 RO 0h Reserved (RSVD)
11 RO 0b Uncore
Discard Timer SERR# Enable (DTSERRE)
Not Applicable or Implemented. Hardwired to 0.
10 RO 0b Uncore
Discard Timer Status (DTSTS)
Not Applicable or Implemented. Hardwired to 0.
9RO 0bUncore
Secondary Discard Timer (SDT)
Not Applicable or Implemented. Hardwired to 0.
8RO 0bUncore
Primary Discard Timer (PDT)
Not Applicable or Implemented. Hardwired to 0.
7RO 0bUncore
Fast Back-to-Back Enable (FB2BEN)
Not Applicable or Implemented. Hardwired to 0.