Datasheet

Processor Configuration Registers
58 Datasheet, Volume 2
7RW-L 1b Uncore
Device 4 Enable (D4EN)
0 = Bus 0 Device 4 is disabled and not visible.
1 = Bus 0 Device 4 is enabled and visible.
This bit will be set to 0b and remain 0b if Device 4 capability is
disabled.
6:5 RO 0h Reserved (RSVD)
4RW-L 1b Uncore
Internal Graphics Engine (D2EN)
0 = Bus 0 Device 2 is disabled and hidden
1 = Bus 0 Device 2 is enabled and visible
This bit will be set to 0b and remain 0b if Device 2 capability is
disabled.
3RW-L 1b Uncore
PEG10 Enable (D1F0EN)
0 = Bus 0 Device 1 Function 0 is disabled and hidden.
1 = Bus 0 Device 1 Function 0 is enabled and visible.
This bit will be set to 0b and remain 0b if PEG10 capability is
disabled.
2RW-L 1b Uncore
PEG11 Enable (D1F1EN)
0 = Bus 0 Device 1 Function 1 is disabled and hidden.
1 = Bus 0 Device 1 Function 1 is enabled and visible.
This bit will be set to 0b and remain 0b if:
• PEG11 capability is disabled by fuses, OR
• PEG11 is disabled by strap (PEG0CFGSEL)
1RW-L 1b Uncore
PEG12 Enable (D1F2EN)
0 = Bus 0 Device 1 Function 2 is disabled and hidden.
1 = Bus 0 Device 1 Function 2 is enabled and visible.
This bit will be set to 0b and remain 0b if:
• PEG12 capability is disabled by fuses, OR
• PEG12 is disabled by strap (PEG0CFGSEL)
0RO 1bUncore
Host Bridge (D0EN)
Bus 0 Device 0 Function 0 may not be disabled and is therefore
hardwired to 1.
B/D/F/Type: 0/0/0/PCI
Address Offset: 54–57h
Reset Value: 0000209Fh
Access: RW-L, RO, RW
Size: 32 bits
BIOS Optimal Default 000000h
Bit Access
Reset
Value
RST/
PWR
Description