Datasheet
Processor Configuration Registers
84 Datasheet, Volume 2
2.5.39 CAPID0_B—Capabilities B Register
Control of bits in this register are only required for customer visible SKU differentiation.
B/D/F/Type: 0/0/0/PCI
Address Offset: E8-EBh
Default Value: 00100000h
Access: RO-FW, RO-KFW
Size: 32 bits
BIOS Optimal Default: 000000h
Bit Access Reset Value
RST/
PWR
Description
31 RO-FW 0h Reserved (RSVD)
30 RO-FW 0b Reserved (RSVD)
29 RO-FW 0b Reserved (RSVD)
28 RO-FW 0b Uncore
SMT Capability (SMT)
This setting indicates whether or not the processor is SMT
capable.
27:25 RO-FW 000b Uncore
Cache Size Capability (CACHESZ)
This setting indicates the supporting cache sizes.
24 RO-FW 0b Reserved (RSVD)
23:21 RO-FW 000b Uncore
DDR3 Maximum Frequency Capability with 100 Memory
(PLL_REF100_CFG)
DDR3 Maximum Frequency Capability with 100 MHz memory.
PCODE will update this field with the value of
FUSE_PLL_REF100_CFG and then apply SSKU overrides.
Maximum allowed memory frequency with 100 MHz reference
clock. Also serves as defeature.
Unlike 133 MHz reference fuses, these are normal 3-bit fields.
0 = 100 MHz ref disabled
1 = Up to DDR-1400 (7 x 200)
2 = Up to DDR-1600 (8 x 200)
3 = Up to DDR-1800 (8 x 200)
4 = Up to DDR-2000 (10 x 200)
5 = Up to DDR-2200 (11 x 200)
6 = Up to DDR-2400 (12 x 200)
7 = No limit (but still limited by %MAX_DDR_FREQ200 to
2600)
20 RO-FW 0b Uncore
PCIe Gen 3 Disable (PEGG3_DIS)
PCODE will update this field with the value of
FUSE_PEGG3_DIS and then apply SSKU overrides.
This is a defeature fuse – an un-programmed device should
have PCIe Gen 3 capabilities enabled.
0 = Capable of running any of the Gen 3-compliant PEG
controllers in Gen 3 mode (Devices 0/1/0, 0/1/1, 0/1/2)
1 = Not capable of running any of the PEG controllers in Gen
3 mode
19 RO-FW 0b Reserved (RSVD)
18 RO-FW 0b Uncore
Additive Graphics Enabled (ADDGFXEN)
0 = Additive Graphics Disabled
1 = Additive Graphics Enabled
17 RO-FW 0b Uncore
Additive Graphics Capable (ADDGFXCAP)
0 = Capable of Additive Graphics
1 = Not capable of Additive Graphics
16 RO-FW 0b Reserved (RSVD)
15:12 RO-FW 0h Reserved (RSVD)