Quad-Core Intel® Xeon® Processor 3300 Series Datasheet February 2009 Version -002 Document Number: 319005-002
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Contents 1 Introduction .............................................................................................................. 9 1.1 Terminology ....................................................................................................... 9 1.1.1 Processor Terminology Definitions ............................................................ 10 1.2 References .......................................................................................................
5.2 5.3 Processor Thermal Features ................................................................................80 5.2.1 Thermal Monitor .....................................................................................80 5.2.2 Thermal Monitor 2 ..................................................................................81 5.2.3 On-Demand Mode ...................................................................................82 5.2.4 PROCHOT# Signal ............................................
3-6 4-1 4-2 5-1 5-2 5-3 5-4 5-5 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 Processor Land Coordinates and Quadrants, Top View............................................... 40 land-out Diagram (Top View – Left Side)................................................................. 42 land-out Diagram (Top View – Right Side)............................................................... 43 Quad-Core Intel® Xeon® Processor 3300 Series Thermal Profile(95W) ................................
Revision History 6 Revision Date Document Number Version Number Revision 319005 1.
Quad-Core Intel® Xeon® Processor 3300 Series Features • Available at 3.16 GHz, 3.00 GHz, 2.83 GHz, 2.66 GHz, and 2.
Datasheet
Introduction 1 Introduction The Quad-Core Intel® Xeon® Processor 3300 Series, like the Quad-Core Intel® Xeon® Processor 3200 Series, is a based on the Intel® CoreTM microarchitecture. The Intel Core microarchitecture combines the performance of previous generation Desktop products with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems.The Quad-Core Intel® Xeon® Processor 3300 Series are 64bit processors that maintain compatibility with IA-32 software.
Introduction 1.1.1 Processor Terminology Definitions Commonly used terms are explained here for clarification: • Quad-Core Intel® Xeon® Processor 3300 Series — Quad core processor in the FC-LGA6 package with two 6 MB L2 cache or two 3 B L2 cache. • Processor — For this document, the term processor is the generic form of the Quad-Core Intel® Xeon® Processor 3300 Series.
Introduction solutions and enables more robust hardware assisted virtualization solutions. More information can be found at: http://www.intel.com/technology/virtualization/ • Platform Environment Control Interface (PECI) — A proprietary one-wire bus interface that provides a communication channel between the processor and chipset components to external monitoring devices. 1.2 References Material and concepts available in the following documents may be beneficial when reading this document: Table 1-1.
Introduction 12 Datasheet
Electrical Specifications 2 Electrical Specifications 2.1 Power and Ground Lands The processor has VCC (power), VTT, and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to VCC, while all VSS lands must be connected to a system ground plane. The processor VCC lands must be supplied the voltage determined by the Voltage IDentification (VID) lands. The signals denoted as VTT provide termination for the front side bus and power to the I/O buffers.
Electrical Specifications properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation. Decoupling guidelines are described in the appropriate platform design guidelines. 2.3 Voltage Identification The Voltage Identification (VID) specification for the processor is defined by the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket.
Electrical Specifications VID VID VID VID VID VID VID VID 7 6 5 4 3 2 1 0 Voltage VID VID VID VID VID VID VID VID Voltage 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 0 1.525 0 1 1 0 1 0 1 0 0.95 0 0 0 1 0 0 0 0 1.5125 0 1 1 0 1 1 0 0 0.9375 0 0 0 1 0 0 1 0 1.5 0 1 1 0 1 1 1 0 0.925 0 0 0 1 0 1 0 0 1.4875 0 1 1 1 0 0 0 0 0.9125 0 0 0 1 0 1 1 0 1.475 0 1 1 1 0 0 1 0 0.9 0 0 0 1 1 0 0 0 1.4625 0 1 1 1 0 1 0 0 0.
Electrical Specifications 2.4 Reserved, Unused, and TESTHI Signals All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands.
Electrical Specifications 2.6 Power Segment Identifier (PSID) Power Segment Identifier (PSID) is a mechanism to prevent booting under mismatched power requirement situations. The PSID mechanism enables BIOS to detect if the processor in use requires more power than the platform voltage regulator (VR) is capable of supplying. For example, a 130W TDP processor installed in a board with a 65W or 95W TDP capable VR may draw too much power and cause a potential VR issue. 2.
Electrical Specifications Storage within these limits will not affect the long-term reliability of the device. For functional operation, refer to the processor case temperature specifications. This rating applies to the processor and does not include any tray or packaging. Failure to adhere to this specification can affect the long term reliability of the processor. 4. 5. 2.7.2 DC Voltage and Current Specification Table 2-3.
Electrical Specifications 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Table 2-4. different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep® Technology, or Extended HALT State). Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data.
Electrical Specifications Table 2-4. VCC Static and Transient Tolerance (Continued) Voltage Deviation from VID Setting (V)1, 2, 3, 4 ICC (A) Maximum Voltage 1.30 mΩ Typical Voltage 1.38 mΩ Minimum Voltage 1.45 mΩ 85 -0.111 -0.136 -0.161 90 -0.117 -0.143 -0.169 95 -0.124 -0.150 -0.176 100 -0.130 -0.157 -0.183 NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.7.3. 2.
Electrical Specifications 3. 2.7.3 The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details.
Electrical Specifications 2.7.4 Die Voltage Validation Overshoot events on processor must meet the specifications in Table 2-5 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit. 2.
Electrical Specifications Table 2-6. FSB Signal Groups Signal Group Signals1 Type GTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY# GTL+ Common Clock I/O Synchronous to BCLK[1:0] ADS#, BNR#, BPM[5:0]#, BPMb[3:0]#, BR0#3, DBSY#, DRDY#, HIT#, HITM#, LOCK# Signals GTL+ Source Synchronous I/O GTL+ Strobes Synchronous to assoc.
Electrical Specifications . Table 2-7.
Electrical Specifications Table 2-9. GTL+ Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 ILI Input Leakage Current N/A ± 100 µA 7 ILO Output Leakage Current N/A ± 100 µA 8 RON Buffer On Resistance 7.49 9.16 Ω 5 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value. 3.
Electrical Specifications 3. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value. VIH and VOH may experience excursions above VTT. However, input signal drivers must comply with the signal quality specifications in Chapter 3. The VTT referred to in these specifications refers to instantaneous VTT. IOL is measured at 0.10 * VTT.
Electrical Specifications Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF. Table 2-13 lists the GTLREF specifications. The GTL+ reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits. For more details on platform design, see the applicable platform design guide. Table 2-13. GTL+ Bus Voltage Definitions Min Typ Max Units Notes1 GTLREF pull up resistor 57.6 * 0.99 57.6 57.6 * 1.
Electrical Specifications 2.9 Clock Specifications 2.9.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor’s core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during manufacturing. The processor supports Half Ratios between 7.5 and 13.
Electrical Specifications The Yorkfield processor will operate at a 1333 MHz FSB frequency (selected by a 333 MHz BCLK[1:0] frequency). Individual processors will only operate at their specified FSB frequency. For more information about these signals, refer to Section 4.2 and the appropriate platform design guidelines. Table 2-15. BSEL[2:0] Frequency Table for BCLK[1:0] 2.9.
Electrical Specifications 2.9.4 BCLK[1:0] Specifications Table 2-16. Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes1 VL Input Low Voltage -0.30 N/A N/A V 2-3 3 VH Input High Voltage N/A N/A 1.15 V 2-3 3 VCROSS(abs) Absolute Crossing Point 0.300 N/A 0.550 V 2-3 2 ∆VCROSS Range of Crossing Points N/A N/A 0.140 V 2-3 - VOS Overshoot N/A N/A 1.4 V 2-3 4 VUS Undershoot -0.
Electrical Specifications 7. Duty Cycle (High time/Period) must be between 40 and 60% . Figure 2-3.
Electrical Specifications 32 Datasheet
Package Mechanical Specifications 3 Package Mechanical Specifications 3.1 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA8) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications 3.1.1 Package Mechanical Drawing The package mechanical drawings are shown in Figure 3-2 and Figure 3-3. The drawings include dimensions necessary to design a thermal solution for the processor. These dimensions include: 1. Package reference with tolerances (total height, length, width, etc.) 2. IHS parallelism and tilt 3. Land dimensions 4. Top-side and back-side component keep-out dimensions 5. Reference datums 6. All drawing dimensions are in mm [in]. 7.
Package Mechanical Specifications Figure 3-2.
Package Mechanical Specifications Figure 3-3.
Package Mechanical Specifications Figure 3-4.
Package Mechanical Specifications 3.1.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 3-2 and Figure 3-3 for keepout zones.
Package Mechanical Specifications 4. 3.1.5 These guidelines are based on limited testing for design characterization. Package Insertion Specifications The processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide. 3.1.6 Processor Mass Specification The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package. 3.
Package Mechanical Specifications 3.1.9 Processor Land Coordinates Figure 3-6 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. . Figure 3-6.
Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 4-1 and Figure 4-2. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view).
Land Listing and Signal Descriptions Figure 4-1.
Land Listing and Signal Descriptions Figure 4-2.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # 44 Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # D25# D13 Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # 46 Signal Buffer Type Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # 48 Signal Buffer Type Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # Signal Buffer Type Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # 50 Signal Buffer Type Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # Signal Buffer Type Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # 52 Signal Buffer Type Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # VSS N6 Signal Buffer Type Table 4-1.
Land Listing and Signal Descriptions Table 4-2. 54 Numerical Land Assignment Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Signal Buffer Type Table 4-2.
Land Listing and Signal Descriptions Table 4-2. 56 Numerical Land Assignment Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # Land Name Signal Buffer Type AJ29 VSS Power/Other AJ3 ITP_CLK1 TAP AJ30 VSS Power/Other Table 4-2.
Land Listing and Signal Descriptions Table 4-2. 58 Numerical Land Assignment Land # Land Name Signal Buffer Type AM18 VCC AM19 VCC Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Table 4-2.
Land Listing and Signal Descriptions Table 4-2. 60 Numerical Land Assignment Signal Buffer Type Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # Land Name Signal Buffer Type H15 FC32 H16 H17 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Land # Land Name Signal Buffer Type Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # Land Name Signal Buffer Type T27 VCC T28 T29 Table 4-2.
Land Listing and Signal Descriptions 4.2 Alphabetical Signals Reference Table 4-3. Signal Description (Sheet 1 of 10) Name A[35:3]# Type Input/ Output Description A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 2 of 10) Name Type Description BPM[5:0]# and BPMb[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# and BPMb[3:0]# should connect the appropriate pins/lands of all processor FSB agents. BPM[3:0]# are associated with core 0.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 3 of 10) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 4 of 10) Name DEFER# DPRSTP# Type Description Input DEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or input/output agent. This signal must connect the appropriate pins/lands of all processor FSB agents.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 5 of 10) Name FCx FERR#/PBE# GTLREF[3:0] HIT# HITM# IERR# Type Other Output Input Input/ Output Input/ Output Output Description FC signals are signals that are available for compatibility with other processors. Refer to the appropriate platform design guide for more information on how these are connected on the motherboard.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 6 of 10) Name INIT# Type Input Description INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 7 of 10) Name Type Description PWRGOOD Input PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 8 of 10) Name Type Description STPCLK# Input STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 9 of 10) Name Description VCC Input VCC are the power pins for the processor. The voltage supplied to these pins is determined by the VID[7:0] pins. VCCA Input VCCA provides isolated power for internal PLLs on previous generation processors. It may be left as a No-Connect on boards supporting the Wolfdale processor.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 10 of 10) Name Type Description Output The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a voltage supply for some signals that require termination to VTT on the motherboard. Refer to the appropriate platform design guide for details on implementation. Output The VTT_SEL signal is used to select the correct VTT voltage level for the processor. This land is connected internally in the package to VSS.
Land Listing and Signal Descriptions 74 Datasheet
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
Thermal Specifications and Design Considerations The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 5-1 instead of the maximum processor power consumption.
Thermal Specifications and Design Considerations Table 5-2. Quad-Core Intel® Xeon® Processor 3300 Series Thermal Profile (95W) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 44.8 50 58.8 2 45.4 52 59.4 4 45.9 54 59.9 6 46.5 56 60.5 8 47.0 58 61.0 10 47.6 60 61.6 12 48.2 62 62.2 14 48.7 64 62.7 16 49.3 66 63.3 18 49.8 68 63.8 20 50.4 70 64.4 22 51.0 72 65.0 24 51.5 74 65.5 26 52.1 76 66.1 28 52.6 78 66.6 30 53.2 80 67.2 32 53.
Thermal Specifications and Design Considerations Figure 5-1. Quad-Core Intel® Xeon® Processor 3300 Series Thermal Profile(95W) 72.0 68.0 64.0 y = 0.28x + 44.8 Tcase (C) 60.0 56.0 52.0 48.0 44.
Thermal Specifications and Design Considerations Table 5-3. Figure 5-2. Quad-Core Intel® Xeon® Processor 3300 Series Thermal Profile (65W) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 49.6 34 63.54 2 50.42 36 64.36 4 51.24 38 65.18 6 52.06 40 66 8 52.88 42 66.82 10 53.7 44 67.64 12 54.52 46 68.46 14 55.34 48 69.28 16 56.16 50 70.1 18 56.98 52 70.92 20 57.8 54 71.74 22 58.62 56 72.56 24 59.44 58 73.38 26 60.26 60 74.2 28 61.08 62 75.
Thermal Specifications and Design Considerations 5.1.2 Thermal Metrology The maximum and minimum case temperatures (TC) for the processor is specified in Table 5-1. This temperature specification is meant to help ensure proper operation of the processor. Figure 5-3 illustrates where Intel recommends TC thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the Yorkfield Processor Thermal and Mechanical Design Guidelines Addendum. Figure 5-3.
Thermal Specifications and Design Considerations periods of TCC activation is expected to be so minor that it would be immeasurable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long-term reliability of the processor.
Thermal Specifications and Design Considerations Figure 5-4. Thermal Monitor 2 Frequency and Voltage Ordering TTM2 Temperature fMAX fTM2 Frequency VID VIDTM2 VID PROCHOT# The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled. It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on demand mode.
Thermal Specifications and Design Considerations 5.2.4 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.
Thermal Specifications and Design Considerations 5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems Fan speed control solutions based on PECI utilize a TCONTROL value stored in the processor IA32_TEMPERATURE_TARGET MSR. The TCONTROL MSR uses the same offset temperature format as PECI though it contains no sign bit. Thermal management devices should infer the TCONTROL value as negative.
Thermal Specifications and Design Considerations that fall under the specification, the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures. There are, however, certain scenarios where the PECI is know to be unresponsive. Prior to a power on RESET# and during RESET# assertion, PECI is not guaranteed to provide reliable thermal data.
Thermal Specifications and Design Considerations 86 Datasheet
Features 6 Features 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 6-1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features Figure 6-1.
Features The system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT Power Down state, the processor will process bus snoops. 6.2.2.2 Extended HALT Powerdown State Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS.
Features 6.2.4.1 HALT Snoop State, Stop Grant Snoop State The processor will respond to snoop transactions on the FSB while in Stop-Grant state or in HALT Power Down state. During a snoop transaction, the processor enters the HALT Snoop State:Stop Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB).
Boxed Processor Specifications 7 Boxed Processor Specifications 7.1 Introduction The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor.
Boxed Processor Specifications 7.2 Mechanical Specifications 7.2.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 7-1 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.
Boxed Processor Specifications Figure 7-3. Top View Space Requirements for the Boxed Processor 95.0 [3.74] 95.0 [3.74] Boxed_Proc_TopView NOTES: 1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Figure 7-4.
Boxed Processor Specifications 7.2.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5 and the Yorkfield Processor Thermal and Mechanical Design Guidelines Addendum for details on the processor weight and heatsink requirements. 7.2.
Boxed Processor Specifications Figure 7-5. Boxed Processor Fan Heatsink Power Cable Connector Description Pin 1 2 3 4 Signal GND +12 V SENSE CONTROL Straight square pin, 4-pin terminal housing with polarizing ribs and friction locking ramp. 0.100" pitch, 0.025" square pin width. Match with straight pin, friction lock header on mainboard. 1 2 3 4 Table 7-1. Fan Heatsink Power and Signal Specifications Description Min Typ Max 11.4 12 12.6 - Maximum fan steady-state current draw — 1.
Boxed Processor Specifications Figure 7-6. Baseboard Power Header Placement Relative to Processor Socket B R110 [4.33] C Boxed_Proc_PwrHeaderPlacement 7.4 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution utilized by the boxed processor. 7.4.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink.
Boxed Processor Specifications Figure 7-7.
Boxed Processor Specifications Figure 7-8. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view) 7.4.2 Variable Speed Fan If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low.
Boxed Processor Specifications Figure 7-9. Boxed Processor Fan Heatsink Set Points Table 7-2. Fan Heatsink Power and Signal Specifications Boxed Processor Fan Heatsink Set Point (ºC) Boxed Processor Fan Speed X ≤ 30 When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment.
Boxed Processor Specifications If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard CPU fan header it will default back to a thermistor controlled mode, allowing compatibility with existing 3-pin baseboard designs. Under thermistor controlled mode, the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet.
Debug Tools Specifications 8 Debug Tools Specifications Refer to the Debug Port Design Guide for UP / DP Systems and the appropriate platform design guidelines for information regarding debug tools specifications. 8.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Yorkfield processor systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces.
Debug Tools Specifications 102 Datasheet
