Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
14 Order Number: 323103-001
10.1 Introduction....................................................................................................370
10.1.1 Types of Reset .....................................................................................370
10.1.2 Trigger, Type, and Domain Association ....................................................370
10.2 Node ID Configuration......................................................................................371
10.3 CPU-Only Reset...............................................................................................372
10.4 Reset Timing Diagrams.....................................................................................373
10.4.1 Cold Reset, CPU-Only Reset Timing Sequences .........................................373
10.4.2 Miscellaneous Requirements and Limitations.............................................373
11.0 Reliability, Availability, Serviceability (RAS) ..........................................................375
11.1 IIO RAS Overview............................................................................................375
11.2 System Level RAS............................................................................................376
11.2.1 Inband System Management..................................................................376
11.2.2 Outband System Management................................................................376
11.3 IIO Error Reporting..........................................................................................376
11.3.1 Error Severity Classification....................................................................377
11.3.1.1 Correctable Errors (Severity 0 Error)........................................377
11.3.1.2 Recoverable Errors (Severity 1 Error)......................................377
11.3.1.3 Fatal Errors (Severity 2 Error).................................................377
11.3.2 Inband Error Reporting..........................................................................378
11.3.2.1 Synchronous Inband Error Reporting........................................378
11.3.2.2 Asynchronous Error Reporting.................................................379
11.3.3 IIO Error Registers Overview..................................................................381
11.3.3.1 Local Error Registers..............................................................382
11.3.3.2 Global Error Registers ............................................................383
11.3.3.3 First and Next Error Log Registers............................................388
11.3.3.4 Error Logging Summary .........................................................388
11.3.3.5 Error Registers Flow...............................................................389
11.3.3.6 Error Containment.................................................................390
11.3.3.7 Error Counters ......................................................................391
11.3.3.8 Stop on Error........................................................................391
11.4 IIO Intel
®
QuickPath Interconnect Interface RAS .................................................391
11.4.1 Intel
®
QuickPath Interconnect Error Detection, Logging, and Reporting........392
11.5 PCI Express* RAS............................................................................................392
11.5.1 PCI Express* Link CRC and Retry............................................................392
11.5.2 Link Retraining and Recovery .................................................................392
11.5.3 PCI Express Error Reporting Mechanism...................................................392
11.5.3.1 PCI Express Error Severity Mapping in IIO ................................392
11.5.3.2 Unsupported Transactions and Unexpected Completions .............393
11.5.3.3 Error Forwarding ...................................................................393
11.5.3.4 Unconnected Ports.................................................................393
11.6 IIO Errors Handling Summary ...........................................................................393
11.7 Hot Add/Remove Support .................................................................................408
11.7.1 Hot Add/Remove Rules..........................................................................409
11.7.2 PCIe Hot Plug.......................................................................................409
11.7.2.1 PCI Express Hot Plug Interface................................................410
11.7.2.2 PCI Express Hot Plug Interrupts...............................................411
11.7.2.3 Virtual Pin Ports (VPP)............................................................413
11.7.2.4 Operation.............................................................................414
11.7.2.5 Miscellaneous Notes...............................................................416
11.7.3 Intel
®
QPI Hot Plug...............................................................................417
12.0 Packaging and Signal Information .........................................................................418
12.1 Signal Descriptions ..........................................................................................418
12.1.1 Intel
®
QPI Signals ................................................................................418
12.1.2 System Memory Interface......................................................................419
12.1.2.1 DDR Channel A Signals ..........................................................419