Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
178 Order Number: 323103-001
3.19.2.4 PCISTS: PCI Status Register
The PCI Status register is a 16-bit status register that reports the occurrence of various
events associated with the primary side of the “virtual” PCI-PCI bridge embedded in
PCI Express ports and also primary side of the other devices on the internal IIO bus.
Register:PCISTS
Bus:0
Device:3
Function:0
Offset:06h
Bit Attr Default Description
15 RW1C 0
Detected Parity Error
This bit is set by a device when it receives a packet on the primary side with
an uncorrectable data error (i.e. a packet with poison bit set or an
uncorrectable data ECC error was detected at the XP-DP interface when ECC
checking is done) or an uncorrectable address/control parity error. The
setting of this bit is regardless of the Parity Error Response bit (PERRE) in
the PCICMD register.
14 RW1C 0
Signaled System Error
1: The device reported fatal/non-fatal (and not correctable) errors it
detected on its PCI Express interface through the ERR[2:0] pins or message
to PCH, with SERRE bit enabled. Software clears this bit by writing a ‘1’ to it.
For Express ports this bit is also set (when SERR enable bit is set) when a
FATAL/NON-FATAL message is forwarded from the Express link to the
ERR[2:0] pins or to PCH via a message. IIO internal ‘core’ errors (like parity
error in the internal queues) are not reported via this bit.
0: The device did not report a fatal/non-fatal error
13 RW1C 0
Received Master Abort
This bit is set when a device experiences a master abort condition on a
transaction it mastered on the primary interface (IIO internal bus). Certain
errors might be detected right at the PCI Express interface and those
transactions might not ‘propagate’ to the primary interface before the error is
detected (e.g. accesses to memory above TOCM in cases where the PCIE
interface logic itself might have visibility into TOCM). Such errors do not
cause this bit to be set, and are reported via the PCI Express interface error
bits (secondary status register). Conditions that cause bit 13 to be set,
include:
• Device receives a completion on the primary interface (internal bus of
IIO) with Unsupported Request or master abort completion Status. This
includes UR status received on the primary side of a PCI Express port on
peer-to-peer completions also.
• Device accesses to holes in the main memory address region that are
detected by the Intel
®
QPI source address decoder.
• Other master abort conditions detected on the IIO internal bus amongst
those listed in Section 6.4.1, “Outbound Address Decoding” (IOH
Platform Architecture Specification)
12 RW1C 0
Received Target Abort
This bit is set when a device experiences a completer abort condition on a
transaction it mastered on the primary interface (IIO internal bus). Certain
errors might be detected right at the PCI Express interface and those
transactions might not ‘propagate’ to the primary interface before the error
is detected (e.g. accesses to memory above VTCSRBASE). Such errors do
not cause this bit to be set, and are reported via the PCI Express interface
error bits (secondary status register). Conditions that cause bit 12 to be set,
include:
• Device receives a completion on the primary interface (internal bus of
IIO) with completer abort completion Status. This includes CA status
received on the primary side of a PCI Express port on peer-to-peer
completions also.
• Accesses to the Intel
®
QPI that returns a failed completion status
• Other completer abort conditions detected on the IIO internal bus
amongst those listed in Section 6.4.2, “Inbound Address Decoding”
(IOH Platform Architecture Specification).