Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 281
PCI Express Non-Transparent Bridge
3.21.1.3 PBAR2XLAT: Primary BAR 2/3 Translate
This register contains a value used to direct accesses into the memory located on the
Secondary side of the NTB made from the Primary side of the NTB through the window
claimed by BAR 2/3 on the primary side. The register contains the base address of the
Secondary side memory window.
Note: There is no hardware enforced limit for this register, care must be taken when setting
this register to stay within the addressable range of the attached system.
Register default: 0000004000000000H
3.21.1.4 PBAR4XLAT: Primary BAR 4/5 Translate
This register contains a value used to direct accesses into the memory located on the
Secondary side of the NTB made from the Primary side of the NTB through the window
claimed by BAR 4/5 on the primary side. The register contains the base address of the
Secondary side memory window.
Note: There is no hardware enforced limit for this register, care must be taken when setting
this register to stay within the addressable range of the attached system.
Register default: 0000008000000000H
Register:PBAR2XLAT
Bar:PB01BASE, SB01BASE
Offset:10h
Bit Attr Default Description
63:nn RWL variable
Primary BAR 2/3 Translate
The aligned base address into Secondary side memory.
Notes:
• Default is set to 256 GB
• These bits appear as RW to SW
(nn-
1) :
12
RO 00h
Reserved
Reserved bits dictated by the size of the memory claimed by the BAR.
Set by Section 3.19.2.12, “PB23BASE: Primary BAR 2/3 Base Address”
11:00 RO variable
Reserved
Reserved bits dictated by the size of the memory claimed by the BAR.
Set by Section 3.19.2.12, “PB23BASE: Primary BAR 2/3 Base Address”
Register:PBAR4XLAT
Bar:PB01BASE, SB01BASE
Offset:18h
Bit Attr Default Description
63:nn RWL variable
Primary BAR 4/5 Translate
The aligned base address into Secondary side memory.
Notes:
• Default is set to 512 GB
• These bits appear as RW to SW
(nn-
1) :
12
RO 00h
Reserved
Reserved bits dictated by the size of the memory claimed by the BAR.
Set by Section 3.19.2.13, “PB45BASE: Primary BAR 4/5 Base Address”
11:00 RO variable
Reserved
Reserved bits dictated by the size of the memory claimed by the BAR.
Set by Section 3.19.2.13, “PB45BASE: Primary BAR 4/5 Base Address”