Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
298 Order Number: 323103-001
3.21.1.26 B2BDOORBELL: Back-to-Back Doorbell
This register is valid when in NTB/NTB configuration. This register is used by the
processor on the primary side of the NTB to generate accesses to the PDOORBELL
register on a second NTB whose Secondary side is connected to the Secondary side of
this NTB. Writing to this register will cause the NTB to generate a PCIe packet that is
sent to the connected NTB’s PDOORBELL register, causing an interrupt to be sent to the
processor on the second system. This mechanism allows inter-system communication
through the pair of NTBs. The B2BBAR0XLAT register must be properly configured to
point to BAR 0/1 on the opposite NTB for this mechanism to function properly.
Register:B2BDOORBELL
Bar:PB01BASE, SB01BASE
Offset:140h
Bit Attr Default Description
15 RV 0b Reserved
14 RV 0b
WC_FLUSH_DONE
‘1’ = This bit will be set by hardware when the IIO write cache has been
flushed.
‘0’ = Hardware upon sensing that bit is set to ‘1’ will schedule a PMW to set
the corresponding bit in the remote NTB (PDOORBELL, bit 14 = ‘1’).
Hardware will then clears this bit after scheduling the PMW.
Note: SW cannot read this register, reads will always return 0
13:00
Bar: Attr
PB01BASE:
RW1S
else: RO
00h
B2B Doorbell Interrupt
These bits are written by the processor on the Primary side of the NTB.
Writing to this register will cause a PCIe packet with the same contents as
the write to be sent to the PDOORBELL register on the a second NTB
connected back-to-back with this NTB, which in turn will cause a doorbell
interrupt to be generated to the processor on the second NTB.
Hardware on the originating NTB clears this register upon scheduling the
PCIE packet.