Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 371
Reset
10.2 Node ID Configuration
A dual-socket Intel
®
Xeon
®
processor C5500/C3500 series system (see Figure 72)
requires a single PCH to be connected to the system. The processor CPU that has the
PCH connected to the DMI port is referred to as the legacy CPU. The DMI port on the
other processor is unused and is referred to as the non-legacy CPU.
A dual socket Intel
®
Xeon
®
processor C5500/C3500 series system requires four Intel
®
QPI node IDs - two for the integrated processor modules (one on each processor) and
two for the integrated IO modules (one on each processor). Thus, each processor
socket is assigned two Intel
®
QPI node IDs.
The node ID assignment is made based on the DMI_PE_CFG# pin.
The DMI_PE_CFG# strap indicates whether the PCH is connected to CPU socket or not.
The Intel
®
Xeon
®
processor C5500/C3500 series CPU that connects to the PCH will be
the legacy CPU and the DMI_PE_CFG# pin will be true for that socket.
The following node IDs will be used by platform:
• 000: Legacy IIO (IIO connected to the PCH)
• 001: Legacy CPU/uncore
• 010: Non-Legacy CPU/uncore
• 100: Non-Legacy IIO (not connected to PCH)
Table 126. Core Trigger, Type, Domain Association
Reset Domain
Reset Trigger Reset Type
PLL VCOs Arrays Straps sampled Fuses sampled Analog I/O Compensation SMBus Protocol Engine Sticky configuration Bits SYRE.SAVCFG, QPILCL.1, Configuration Bit Tri-statable Outputs Fuse Downloader Array Initialization Engines Misc. State Machines PCI Express Logic QPI Link Logic Layer DMI Logic Internal CPU Reset (RESETO_N) Signal
COREPWRGOOD signal de-assertion Power good xxx xxxxxxxxxxx
PLTRST# assertion Warm x x x x x x x
Receive Link Initialization Packet Link QPI x
IIO.BCTRL.Secondary Bus Reset PCI Express x
SMBus protocol SMBus x
IIO.SYRE.CPURESET CPU Warm x