Datasheet

Reliability, Availability, Serviceability (RAS)
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
392 Order Number: 323103-001
11.4.1 Intel
®
QuickPath Interconnect Error Detection, Logging, and
Reporting
The IIO implements Intel
®
QuickPath Interconnect error detection and logging that follows the IIO
local and global error reporting mechanism described in this chapter. These registers provide the
control and logging of the errors detected on the Intel
®
QuickPath Interconnect interface. The IIO
Intel
®
QuickPath Interconnect error detection, logging, and reporting provides the following features:
• Error indication by interrupt (CPEI, SMI, NMI).
• Error indication by response status field in response packets.
• Error indication by data poisoning.
• Error indication by error pin.
• Hierarchical time-out for fault diagnosis and FRU isolation.
For the physical and link layers there is an error log register per port. In the protocol and routing
layers, there is a single error log.
11.5 PCI Express* RAS
The PCI Express Base Specification, Revision 2.0 defines a standard set of error reporting
mechanisms and the IIO supports them all, including the error poisoning and Advanced Error
Reporting. Any exceptions are called out where appropriate. The IIO PCIe ports support the following
features:
• Link level CRC and retry.
• Dynamic link width reduction on link failure.
• PCIe error detection and logging.
• PCIe error reporting.
11.5.1 PCI Express* Link CRC and Retry
PCIe supports link CRC and link level retry for CRC errors. See the PCI Express Base Specification,
Revision 2.0 for details.
11.5.2 Link Retraining and Recovery
The PCIe interface provides a mechanism to recover from a failed link. The PCIe link is capable of
operating in different link width. The IIO will support PCIe port operation in x8, x4, x2, and x1. In
case of a persistent link failure, the PCIe link can fall back to a smaller link width in and attempt to
recover from the error. A PCIe x8 link can fall back to a x4 link. A PCIe x4 can fall back to x2 link, and
then to X1 link. This mechanism enables the continuation of system operation in case of PCIe link
failures. See the PCIe Base Specification, Revision 1.0a for details.
11.5.3 PCI Express Error Reporting Mechanism
The IIO supports standard and advanced PCIe error reporting for its PCIe ports. Since the IIO belongs
to the root complex, its PCIe ports are implemented as root ports. See the PCI Express Base
Specification, Revision 2.0 for details of PCIe error reporting. The following sections highlight the
important aspects of PCIe error reporting mechanism.
11.5.3.1 PCI Express Error Severity Mapping in IIO
The errors reported to the IIO PCIe root port can optionally signal to the IIO global error logic
according to their severities through the programming of the PCIe root control register (ROOTCON).
When system error reporting is enabled for the specific PCIe error type, the IIO maps the PCIe error