Datasheet

Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
98 Order Number: 323103-001
• The master holds SCL continuously high for 50 us.
• Force a platform reset.
Note: Since the configuration registers are affected by the reset pin, SMBus masters will not
be able to access the internal registers while the system is in reset.
2.3.9 Configuration and Memory Read Protocol
Configuration and memory reads are accomplished through an SMBus write(s) and
later followed by an SMBus read. The write sequence is used to initialize the Bus
Number, Device, Function, and Register Number for the configuration access. The
writing of this information can be accomplished through any combination of the
supported SMBus write commands (Block, Word or Byte). The Internal Command field
for each write should specify Read DWord.
After all the information is set up, the last write (End bit is set) initiates an internal
configuration read. The slave will assert a busy bit in the status register and release the
link with an acknowledge (ACK). The master SMBus will perform the transaction
sequence for reading the data, however, the master must observe the status bit [7]
(busy) to determine if the data is valid. This is due to the PCIe time-outs that may be
long, causing an SMBus spec violation. The SMBus master must poll the busy bit to
determine when the pervious read transaction has completed.
If an error occurs then the status byte will report the results. This field indicates
abnormal termination and contains status information such as target abort, master
abort, and time-outs.
Examples of configuration reads are illustrated below. All of these examples have PEC
(Packet Error Code) enabled. If the master does not support PEC, then bit 4 of the
command would be cleared and no PEC byte exists in the communication streams. For
the definition of the diagram conventions below, see the SMBus Specification,
Revision 2.0. For SMBus read transactions, the last byte of data (or the PEC byte if
enabled) is NACKed by the master to indicate the end of the transaction.