Datasheet

24 Intel
®
Xeon
®
Processor E7-8800/4800/2800 Product Families
September 2012 Specification Update
which BIOS code runs on, may have one thread take the power event and the other
thread not take the power event, resulting in a system hang.
Implication: As a result of this erratum, the system may hang after BIOS initiates a system quiesce flow.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
BP31. Uncorrected Memory Error Detected by a Memory Patrol Scrub With
SMI Generated by Other Memory Controllers May Cause MCE/System
Management Interrupt Race Condition
Problem: BIOS may configure a System Management Interrupt to be signaled when the patrol
scrub engine has reached the end of scrubbing a memory range. If the System
Management Interrupt is generated while an uncorrected error is detected by another
memory patrol scrub engine, it may result MCE/SMI race condition which may lead to
system shutdown.
Implication: Due to this erratum, the system may shut down.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
BP32. Broken trace to either the P or the N lane of the Intel
®
SMI forwarded
clock differential pair may result in loss of forwarded clock but not
always lead to clock lane failover.
Problem: If either only the P or the N lane of the Intel
®
SMI forwarded clock is broken, then
processor is capable of detecting minimum differential swing on the clock lane, thus
resulting in the processor to assume that the forwarded clock still exists. Consequently,
the processor will proceed to the Intel
®
SMI link training phase.
Implication: If the processor proceeds to the link training phase, then based on observations, it is
possible that the Intel
®
SMI link may fail to train even after seven retry attempts and
continue to remain in RESET state; or, if the link successfully reached L0 state, then the
link may be unstable and shortly return to Disable_a state. However, if the P and N
lanes of the forwarded clock differential pair are both broken due to board trace issues,
then the clock failover mechanism on Intel
®
SMI channel has been found to operate
successfully as expected.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BP33. Package C3/C6 with Memory Self-refresh Enabled May Cause False
Error Logging
Problem: When the processor is in Package C3/C6 with Memory Self Refresh, correctable errors
may occur resulting in a system management interrupt (SMI). The SMI generation may
result in a false error being logged in the IA32_MC6_STATUS (MSR 0x419) register.
Implication: Due to this erratum, a false error may be reported in IA32_MC6_STATUS register.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
BP34. Performance Monitor WOKEN Event May Under Count
Problem: Performance Monitoring counter WOKEN (Event: 0x0F8) counts the number of cores
woken up from core C-states. Due to this erratum, the WOKEN event may not count
the cores that are woken up from core C-states due to Trusted Execution Technology
transactions.