Mobile Intel® Atom™ Processor N270 Single Core Datasheet May 2008 Document Number: 320032-001
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
Contents 1 Introduction .....................................................................................................6 1.1 1.2 1.3 2 Low Power Features ........................................................................................10 2.1 2.2 2.3 2.4 2.5 3 4.2 4.3 Package Mechanical Specifications ..........................................................33 4.1.1 Package Mechanical Drawings ...................................................34 Processor Pin-out Assignment .............
Figures Figure Figure Figure Figure 1. 2. 3. 4. Thread Low-power States ...................................................................11 Package Low-power States..................................................................11 Active VCC and ICC Processor Loadline .................................................28 Deeper Sleep VCC and ICC Processor Loadline .......................................
Revision History Document Number Revision Number 320032 001 Description Initial release.
Introduction 1 Introduction The Intel® Atom™ Processor N270 (code named Mobile Diamondville) is built on 45nanometer process technology — the first generation of low-power IA-32 microarchitecture specially designed for Netbook’08 Platform. In this platform, the processor supports Intel® 945GSE chipset with the I/O Controller Hub - Intel 82801GBM. Note: Throughout this document, the Intel® Atom™ Processor N270 is referred as processor. 1.
Introduction 1.2 Terminology Term Datasheet Definition # A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a non-maskable interrupt has occurred.
Introduction Term 8 Definition VCC,BOOT Default VCC Voltage for Initial Power Up. VCCP AGTL+ Termination Voltage. VCCA PLL Supply voltage. VCCDPRSLP VCC at Deeper Sleep (C4). VCCF Fuse Power Supply. ICCDES ICC for Mobile Intel® Atom™ Processor N270 Recommended Design Target (Estimated). ICC ICC for Mobile Intel® Atom™ Processor N270 is the number that can be use as a reflection on a battery life estimates. IAH, ICC Auto-Halt ISGNT ICC Stop-Grant. IDSLP ICC Deep Sleep.
Introduction 1.3 References Material and concepts available in the following documents may be beneficial when reading this document. Table 1. References Document No./Location Document Intel® 64 and IA-32 Architectures Software Developer's Manuals • Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture http://www.intel.
Low Power Features 2 Low Power Features 2.1 Clock Control and Low-power States The processor supports low power states at the thread level and the package level. A thread may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, and C4 low power states. Package low power states include Normal, Stop Grant, Stop Grant Snoop, Sleep and Deep Sleep.
Low Power Features Figure 1. Thread Low-power States Figure 2.
Low Power Features Table 2. Coordination of Thread Low-power States at the Package Level Package State2 Thread State C0 C11 C2 C4 Normal Normal Normal Normal Normal AutoHalt AutoHalt AutoHalt C2 Normal AutoHalt Stop-Grant Stop-Grant C4 Normal AutoHalt Stop-Grant Deeper Sleep /Intel® Enhanced Deeper Sleep C0 C1 1 NOTES: 1. AutoHALT or MWAIT/C1. 2. To enter a package state, both threads must be in a common low power state.
Low Power Features 2.1.1.3 Thread C1/MWAIT Power-down State C1/MWAIT is a low-power state entered when the processor thread executes the MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state except that Monitor events can cause the processor to return to the C0 state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals, Volume 2A: Instruction Set Reference, A-M and Volume 2B: Instruction Set Reference, N-Z, for more information. 2.1.1.
Low Power Features termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state. RESET# causes the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#, SLP#, DPSLP#, and DPRSTP# pins must be de-asserted prior to RESET# de-assertion. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted after the de-assertion of SLP#.
Low Power Features While in the Sleep state, the processor is capable of entering an even lower power state, the Deep Sleep state, by asserting the DPSLP# pin (see Section 2.1.2.5). While the processor is in the Sleep state, the SLP# pin must be de-asserted if another asynchronous FSB event needs to occur. 2.1.2.5 Deep Sleep State The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep state.
Low Power Features L2 cache has been reduced to zero ways and completely shut down. The following events occur when the processor enters Intel Enhanced Deeper Sleep state: 2.2 • The processor issues a P_LVL4 I/O read or an MWAIT(C4) instruction and then progressively reduces the L2 cache to zero. • The processor drives the VID code corresponding to the Intel Enhanced Deeper Sleep state core voltage on the VID [6:0] pins.
Low Power Features 2.3 Enhanced Intel SpeedStep® Technology The processor features Enhanced Intel SpeedStep Technology. Following are the key features of Enhanced Intel SpeedStep Technology: Datasheet • Multiple voltage and frequency operating points provide optimal performance at the lowest power.
Low Power Features 2.4 Enhanced Low-Power States Enhanced low-power states (C1E, C2E, C4E) optimize for power by forcibly reducing the performance state of the processor when it enters a package low-power state. Instead of directly transitioning into the package low-power state, the enhanced package low-power state first reduces the performance state of the processor by performing an Enhanced Intel SpeedStep Technology transition down to the lowest operating point.
Low Power Features 2.5 FSB Low Power Enhancements The processor incorporates FSB low power enhancements: • BPRI# control for address and control input buffers • Dynamic Bus Parking • Dynamic On Die Termination disabling • Low VCCP (I/O termination voltage) The processor incorporates the DPWR# signal that controls the data bus input buffers on the processor.
Electrical Specifications 3 Electrical Specifications 3.1 Power and Ground Pins For clean, on-chip power distribution, the processor will have a large number of VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. The processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins. 3.
Electrical Specifications Datasheet VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 0 1 0 0 0 1 1 1.0625 0 1 0 0 1 0 0 1.0500 0 1 0 0 1 0 1 1.0375 0 1 0 0 1 1 0 1.0250 0 1 0 0 1 1 1 1.0125 0 1 0 1 0 0 0 1.0000 0 1 0 1 0 0 1 0.9875 0 1 0 1 0 1 0 0.9750 0 1 0 1 0 1 1 0.9625 0 1 0 1 1 0 0 0.9500 0 1 0 1 1 0 1 0.9375 0 1 0 1 1 1 0 0.9250 0 1 0 1 1 1 1 0.9125 0 1 1 0 0 0 0 0.
Electrical Specifications 22 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 1 0 0 0 1 1 0 0.6250 1 0 0 0 1 1 1 0.6125 1 0 0 1 0 0 0 0.6000 1 0 0 1 0 0 1 0.5875 1 0 0 1 0 1 0 0.5750 1 0 0 1 0 1 1 0.5625 1 0 0 1 1 0 0 0.5500 1 0 0 1 1 0 1 0.5375 1 0 0 1 1 1 0 0.5250 1 0 0 1 1 1 1 0.5125 1 0 1 0 0 0 0 0.5000 1 0 1 0 0 0 1 0.4875 1 0 1 0 0 1 0 0.4750 1 0 1 0 0 1 1 0.4625 1 0 1 0 1 0 0 0.
Electrical Specifications 3.4 Catastrophic Thermal Protection The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor.
Electrical Specifications 3.7 FSB Signal Groups To simplify the following discussion, the FSB signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
Electrical Specifications Signal Group Open Drain Output Type Synchronous Signals1 TDO to TCK FSB Clock Clock Power/Other BCLK [1:0] COMP [3:0], HFPLL (old name is DBR#2), CMREF, GTLREF, TEST2/Dclk, TEST1/Aclk, THERMDA, THERMDC, VCC, VCCA, VCCP, VCC_SENSE, VSS, VSS_SENSE, VCCQ [1:0], VCCPC6 NOTES: 1. Refer to Chapter 4 for signal descriptions and termination requirements. 2.
Electrical Specifications Table 6. Processor Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes1,5 -40 85 °C 2 TSTORAGE Processor Storage Temperature VCC, VCCP Any Processor Supply Voltage with Respect to VSS -0.3 1.10 V 1 VinAGTL+ AGTL+ Buffer DC Input Voltage with Respect to VSS -0.1 1.10 V 1, 2 VinAsynch_CMOS CMOS Buffer DC Input Voltage with Respect to VSS -0.1 1.10 V 1, 2 NOTES: 1. This rating applies to the processor and does not include any tray or packaging.
Electrical Specifications Table 7. Voltage and Current Specifications for the Processors Symbol Parameter Min Typ Max Unit 132.63 133.33 133.37 MHz Notes13 FSB Frequency BCLK Frequency VCCHFM VCC at Highest Frequency Mode (HFM) AVID - 1.10 V 1, 2, 11 VCCLFM VCC at Lowest Frequency Mode (LFM) 0.75 — AVID V 1, 2 VCC,BOOT Default VCC Voltage for Initial Power Up — 1.20 — V 2, 6 VCCP AGTL+ Termination Voltage 1.00 1.05 1.10 V VCCA PLL Supply voltage 1.425 1.5 1.
Electrical Specifications 3. 4. 5. 6. 7. 8. 9. 10. 11. impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. Specified at 90°C TJ. Specified at the nominal VCC. Measured at the bulk capacitors on the motherboard. VCC,BOOT tolerance is shown in Figure 3 and Figure 4. Based on simulations and averaged over the duration of any change in current. Specified by design/characterization at nominal VCC.
Electrical Specifications Figure 4. Deeper Sleep VCC and ICC Processor Loadline Table 8. FSB Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes1 VIH Input High Voltage — — 1.15 V 7, 8 VOH Input Low Voltage — — -0.3 V 7, 8 0.3 — 0.55 V 2, 7, 9 VCROSS Crossing Voltage ΔVCROSS Range of Crossing Points — — 140 mV 2, 7, 5 VSWING Differential Output Swing 300 — — mV 6 Input Leakage Current -5 — +5 µA 3 Pad Capacitance 1.2 1.45 2.
Electrical Specifications Table 9. AGTL+ Signal Group DC Specifications Symbol VCCP Parameter I/O Voltage Min Typ Max Unit 1.00 1.05 1.10 V Notes1 GTLREF GTL Reference Voltage — 2/3 VCCP — V 6 RCOMP Compensation Resistor 27.23 27.5 27.78 Ω 10 RODT Termination Resistor — 55 — Ω 11 VIH Input High Voltage GTLREF+0.10 VCCP VCCP+0.10 V 3,6 VIL Input Low Voltage -0.10 0 GTLREF–0.10 V 2,4 VOH Output High Voltage VCCP–0.
Electrical Specifications Table 10. Legacy CMOS Signal Group DC Specifications Symbol Min Typ Max Unit 1.00 1.05 1.10 V Notes1 VCCP I/O Voltage VIH Input High Voltage 0.7*VCCP VCCP VCCP+0.1 V 2 VIL Input Low Voltage CMOS -0.10 0.00 0.3*VCCP V 2, 3 VOH Output High Voltage 0.9*VCCP VCCP VCCP+0.1 V 2 VOL Output Low Voltage -0.10 0 0.1*VCCP V 2 IOH Output High Current 1.5 — 4.1 mA 5 IOL Output Low Current 1.5 — 4.
Electrical Specifications Table 11. Open Drain Signal Group DC Specifications Symbol Parameter Min Typ Max Unit Notes1 3 VOH Output High Voltage VCCP-–5% VCCP VCCP+5% V VOL Output Low Voltage 0 — 0.20 V IOL Output Low Current 16 — 50 mA 2 ILO Output Leakage Current — — ±200 µA 4 Cpad Pad Capacitance 1.9 2.2 2.45 pF 5 NOTES: 1. 2. 3. 4. 5. Unless otherwise noted, all specifications in this table apply to all processor frequencies. Measured at 0.2 VCCP.
Package Mechanical Specifications and Pin Information 4 Package Mechanical Specifications and Pin Information This chapter provides the package specifications, pin-out assignments, and signal description. 4.1 Package Mechanical Specifications The processor is available in 512 KB, 437 pins in FCBGA8 package. The package dimensions are shown in Figure .
Package Mechanical Specifications and Pin Information 4.1.1 Package Mechanical Drawings Figure 5. Package Mechanical Drawing 4.2 Processor Pin-out Assignment Figure are graphic representations of the processor pin-out assignments. Table 12 lists the pin-out by signal name.
Package Mechanical Specifications and Pin Information Figure 6.
Package Mechanical Specifications and Pin Information Table 12.
Package Mechanical Specifications and Pin Information Datasheet Signal Name Ball # Signal Name Ball # Signal Name Ball # D [40]# G3 DEFER# T21 NC K4 D [41]# H2 DINV [0]# W16 NC K5 D [42]# N2 DINV [1]# Y6 NC M15 D [43]# L2 DINV [2]# L1 NC L16 D [44]# M3 DINV [3]# C5 PRDY# K18 D [45]# J2 DPRSTP# R18 PREQ# J16 D [46]# H1 DPWR# U4 PROCHOT# G17 D [47]# J1 DRDY# T19 PWRGOOD V17 D [48]# C2 DSTBN [0]# Y14 REQ [0]# N21 D [49]# G2 DSTBN [1]# Y4 REQ [1]
Package Mechanical Specifications and Pin Information 38 Signal Name Ball # Signal Name Ball # Signal Name Ball # VCCPC63 F13 VCC F11 VCCQ0 A9 VCCPC64 F14 VCC F12 VCCQ0 B9 SLP# N18 VCC G10 VCCSENSE C13 SMI# U17 VCC G11 VID [0] F15 STPCLK# R16 VCC G12 VID [1] D16 TCK M17 VCC H10 VID [2] E18 TDI N16 VCC H11 VID [3] G15 TDO M16 VCC H12 VID [4] G16 EXTREF M6 VCC J10 VID [5] E17 THERMTRIP# H17 VCC J11 VID [6] G18 THRMDA E4 VCC J12 VSS A2 T
Package Mechanical Specifications and Pin Information Datasheet Signal Name Ball # Signal Name Ball # Signal Name Ball # VSS D21 VSS J13 VSS P3 VSS E3 VSS J17 VSS P4 VSS E6 VSS K1 VSS P5 VSS E7 VSS K6 VSS P6 VSS E8 VSS K7 VSS P7 VSS E15 VSS K9 VSS P9 VSS E16 VSS K13 VSS P13 VSS E19 VSS K15 VSS P15 VSS F4 VSS K21 VSS P16 VSS F5 VSS L3 VSS P18 VSS F6 VSS L4 VSS P19 VSS F7 VSS L5 VSS R1 VSS F17 VSS L6 VSS R5 VSS F18 VSS L7
Package Mechanical Specifications and Pin Information 40 Signal Name Ball # Signal Name Ball # Signal Name Ball # VSS U19 VSS AA4 VTT L14 VSS V1 VSS AA7 VTT M8 VSS V4 VSS AA10 VTT M14 VSS V6 VSS AA12 VTT N8 VSS V7 VSS AA15 VTT N14 VSS V8 VSS AA18 VTT P8 VSS V13 VSS AA19 VTT P14 VSS V14 VSS AA20 VTT R8 VSS V18 VSSSENSE D13 VTT R14 VSS V21 VTT C9 VTT T8 VSS W1 VTT D9 VTT T14 VSS W5 VTT E9 VTT U8 VSS W8 VTT F8 VTT U9 VSS W11
Package Mechanical Specifications and Pin Information 4.3 Signal Description Table 13. Signal Description Signal Name Type Description A [31:3]# (Address) defines a 232-byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. A [31:3]# A20M# I/O I In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the processor FSB.
Package Mechanical Specifications and Pin Information Signal Name Type Description BPM [0]# O BPM [1]# I/O BPM [2]# O BPM [3]# I/O BPM [3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM [3:0]# should connect the appropriate pins of all FSB agents. This includes debug or performance monitoring tools.
Package Mechanical Specifications and Pin Information Signal Name DBSY# DEFER# Type Description I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the FSB to indicate that the data bus is in use. The data bus is released after DBSY# is de-asserted. This signal must connect the appropriate pins on both FSB agents. I DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion.
Package Mechanical Specifications and Pin Information Signal Name Type Description Data strobe used to latch in D [63:0]#. DSTBP [3:0]# FERR#/PBE# I/O O Signals Associated Strobe D [15:0]# DINV [0]#, DSTBP [0]# D [31:16]# DINV [1]#, DSTBP [1]# D [47:32]# DINV [2]#, DSTBP [2]# D [63:48]# DINV [3]#, DSTBP [3]# FERR# (Floating-point Error)PBE#(Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#.
Package Mechanical Specifications and Pin Information Signal Name IERR# IGNNE# Type Description O IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.
Package Mechanical Specifications and Pin Information Signal Name Type Description Lock# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of both FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. LOCK# I/O PRDY# O Probe Ready signal used by debug tools to request debug operation of the processor.
Package Mechanical Specifications and Pin Information Signal Name RESET# Type I Description Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both FSB agents will de-assert their outputs within two clocks.
Package Mechanical Specifications and Pin Information Signal Name TDO Description O TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. Please contact your Intel representative for more implementation details. TEST[1:4] Refer to the appropriate platform design guide for further TEST1, TEST2, TEST3, and TEST4 termination requirements and implementation details. All TEST signals can be left as No Connects.
Package Mechanical Specifications and Pin Information Signal Name VCC_SENSE VSS_SENSE Type Description O VCCSENSE is an isolated low impedance connection to processor core power (VCC). It can be used to sense or measure power near the silicon with little noise. Please contact your Intel representative for more implementation details. O VSS_SENSE is an isolated low impedance connection to processor core VSS. It can be used to sense or measure ground near the silicon with little noise.
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations The processor requires a thermal solution to maintain temperatures within operating limits. A complete thermal solution includes both component and system level thermal management features.
Thermal Specifications and Design Considerations The processor incorporates three methods of monitoring die temperature: the Digital Thermal Sensor, Intel Thermal Monitor, and the Thermal Diode. The Intel Thermal Monitor (detailed in Section 5.2) must be used to determine when the maximum specified processor junction temperature has been reached. 5.
Thermal Specifications and Design Considerations Table 15. Thermal Diode Interface Signal Name Pin/Ball Number Signal Description THERMDA E4 Thermal diode anode THERMDC E5 Thermal diode cathode Table 16. Thermal Diode Parameters using Transistor Model Symbol Min Typ Max Unit Notes Forward Bias Current 5 — 200 μA 1 IE Emitter Current 5 — 200 μA 1 nQ Transistor Ideality 0.997 1.001 1.015 2,3,4 0.25 — 0.65 2,3 2.79 4.52 6.
Thermal Specifications and Design Considerations 5.2 Intel® Thermal Monitor The Intel Thermal Monitor helps control the processor temperature by activating the TCC (Thermal Control Circuit) when the processor silicon reaches its maximum operating temperature. The temperature at which the Intel Thermal Monitor activates the TCC is not user configurable.
Thermal Specifications and Design Considerations limit and subsequently searches for the highest possible operating point. Please ensure this feature is enabled and supported in the BIOS. Also with EMTTM enabled, the operating system can request the processor to throttling to any point between Intel Dynamic Acceleration frequency and Super LFM frequency as long as these features are enabled in the BIOS and supported by the processor.
Thermal Specifications and Design Considerations Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or de-assertion of PROCHOT#. PROCHOT# will not be asserted when the processor is in the Stop Grant, Sleep, Deep Sleep, and Deeper Sleep low power states; hence, the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification.
Thermal Specifications and Design Considerations Note: The digital thermal sensor (DTS) accuracy is in the order of -5°C ~ +10°C around 90°C; it deteriorates to ±10°C at 50°C. The DTS temperature reading saturates at some temperature below 50°C. Any DTS reading below 50°C should be considered to indicate only a temperature below 50°C and not a specific temperature. External thermal sensor with “BJT” model is required to read thermal diode temperature. 5.3.
Thermal Specifications and Design Considerations consumption. Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP.
