Datasheet

Table 4. Supported DDR3L / DDR3L-RS SO-DIMM Module Configurations Per Channel
Raw
Card
Version
SO-
DIMM
Capacity
SDRAM
Organizati
on
SDRAM
Density
# of
SDRAM
Devices
# of
Ranks
# of
Row/Col
Address
Bits
# of
SDRAM
Banks
Page Size
A 2 GB 128 M x 16 2 Gb 8 2 14/10 8 8 KB
A 4 GB 256 M x 16 4 Gb 8 2 15/10 8 8 KB
B 2 GB 256 M x 8 2 Gb 8 1 15/10 8 8 KB
B 4 GB 512 M x 8 4 Gb 8 1 16/10 8 8 KB
C 1 GB 128 M x16 2 Gb 4 1 14/10 8 8 KB
C 2 GB 256 M x16 4 Gb 4 1 15/10 8 8 KB
F 4 GB 256 M x8 2 Gb 16 2 15/10 8 8 KB
F 8 GB 512 M x8 4 Gb 16 2 16/10 8 8 KB
Table 5. Supported DDR3L/DDR3L-RS Memory Down Configurations Per Channel
Memory
Capacity
SDRAM
Organization
SDRAM
Density
# of
SDRAM
Devices
# of
Ranks
# of
Row/Col
Address
Bits
# of
SDRAM
Banks
Page Size
1 GB 128 M x 16 2 Gb 4 1 14/10 8 8 KB
2 GB 256 M x 16 4 Gb 4 1 15/10 8 8 KB
4 GB
256 M x 16
DDP
8 Gb 4 2 15/10 8 8 KB
Note: DDP - Stacked/Dual-Die Package
Table 6. Supported LPDDR3 Memory Down Configurations Per Channel
Memory
Capacity
DRAM
Organiza
tion
DRAM
Die
Density
DRAM
Package
Density
# of
DRAM
Devices
# of
Ranks
# of
Row/Col
Address
Bits
# of
DRAM
Banks
Page
Size
2 GB SDP x 32 4 Gb 4 Gb 2 1 14/10 8 8 KB
4 GB DDP x 32 4 Gb 8 Gb 2 1 15/10 8 8 KB
Note: SDP - Singl Die Package; DDP - Stacked/Dual-Die Package
System Memory Timing Support
• tCL = CAS Latency
• tRCD = Activate Command to READ or WRITE Command delay
• tRP = PRECHARGE Command Period
• tCWL = CAS Write Latency
• Command Signal modes = 1N indicates a new command may be issued every
clock and 2N indicates a new command may be issued every 2 clocks. Command
launch mode programming depends on the transfer rate and memory
configuration.
2.1.2
Interfaces—Processor
5th Generation Intel
®
Core
™
Processor Family, Intel
®
Core
™
M Processor Family, Mobile Intel
®
Pentium
®
Processor Family, and
Mobile Intel
®
Celeron
®
Processor Family
March 2015 Datasheet – Volume 1 of 2
Order No.: 330834-004v1 19