Datasheet

• The processor supports streaming any 3 independent and simultaneous display
combination of DisplayPort*/HDMI*/eDP*/ monitors. In the case of 3
simultaneous displays, two High Definition Audio streams over the digital display
interfaces are supported.
• Each digital port is capable of driving resolutions up to 3840x2160 at 60 Hz using
4 lanes at link data rate HBR2 through DisplayPort* and 4096x2304 at 24 Hz
using HDMI*. Use of active level shifter is required to obtain maximum HDMI
resolution.
• DisplayPort* Aux CH, DDC channel, Panel power sequencing, and HPD are
supported through the PCH.
Figure 3. Processor Display Architecture
Memory \ Config Interface
Display
Pipe A
Display
Pipe B
Display
Pipe C
Panel Fitting
HD Audio
Controller
Transcoder A
DP / HDMI
Timing, VDIP
Transcoder B
DP / HDMI
Timing, VDIP
Transcoder C
DP / HDMI
Timing, VDIP
eDP* Mux
Transcoder eDP*
DP encoder
Timing, VDIP
DPT, SRID
Port Mux
Audio
Codec
DP
Aux
eDP
X4 eDP
PCH Display Control Signals
DDI Ports B and C
X4 DP /
HDMI
X4 DP /
HDMI
Display is the presentation stage of graphics. This involves:
• Pulling rendered data from memory
• Converting raw data into pixels
• Blending surfaces into a frame
• Organizing pixels into frames
• Optionally scaling the image to the desired size
• Re-timing data for the intended target
• Formatting data according to the port output standard
DisplayPort*
DisplayPort* is a digital communication interface that uses differential signaling to
achieve a high-bandwidth bus interface designed to support connections between PCs
and monitors, projectors, and TV displays.
Processor—Interfaces
5th Generation Intel
®
Core
™
Processor Family, Intel
®
Core
™
M Processor Family, Mobile Intel
®
Pentium
®
Processor Family, and
Mobile Intel
®
Celeron
®
Processor Family
Datasheet – Volume 1 of 2 March 2015
26 Order No.: 330834-004v1