Datasheet

Processor Internal Pull-Up / Pull-Down Terminations
Table 37. Processor Internal Pull-Up / Pull-Down Terminations
Signal Name Pull Up / Pull Down Rail Value
BPM[7:0] Pull Up Vcc
IO
40–60 Ω
PREQ# Pull Up Vcc
IO
40–60 Ω
PROC_TDI Pull Up Vcc
ST
30–70 Ω
PROC_TMS Pull Up Vcc
ST
30–70 Ω
CFG[19:0] Pull Up Vcc
ST
5–8 kΩ
CATERR# Pull Up Vcc
ST
30–70 Ω
Note: The Configuration Signals (CFG) should be be pulled to a stable logic value up to PLTRST# de-
assertion.
6.12
Signal Description—Processor
5th Generation Intel
®
Core
™
Processor Family, Intel
®
Core
™
M Processor Family, Mobile Intel
®
Pentium
®
Processor Family, and
Mobile Intel
®
Celeron
®
Processor Family
March 2015 Datasheet – Volume 1 of 2
Order No.: 330834-004v1 79