Datasheet
Symbol Parameter Min Typ Max Units Notes
1
SM_RCOMP1 Data COMP Resistance 118.8 120 121.2 Ω 8
SM_RCOMP2 ODT COMP Resistance 99 100 101 Ω 8
Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
IL
is defined as the maximum voltage level at a receiving agent that will be interpreted as a
logical low value.
3. V
IH
is defined as the minimum voltage level at a receiving agent that will be interpreted as a
logical high value.
4. V
IH
and V
OH
may experience excursions above V
DDQ
. However, input signal drivers must comply
with the signal quality specifications.
5. This is the pull up/down driver resistance.
6. R
TERM
is the termination on the DIMM and in not controlled by the processor.
7. The minimum and maximum values for these signals are programmable by BIOS to one of the
two sets.
8. SM_RCOMPx resistance must be provided on the system board with 1% resistors. SM_RCOMPx
resistors are to V
SS
.
9. SM_DRAMPWROK rise and fall time must be < 50 ns measured between V
DDQ
*0.15 and V
DDQ
*0.47.
10.SM_VREF is defined as V
DDQ
/2.
11.Maximum-minimum range is correct; however, center point is subject to change during MRC
boot training.
12.Processor may be damaged if V
IH
exceeds the maximum voltage for extended periods.
13.The MRC during boot training might optimize R
ON
outside the range specified.
14.R
ON
tolerance is preliminary and might be subject to change.
Table 44. LPDDR3 Signal Group DC Specifications
Symbol Parameter Min Typ. Max Unit Note
V
IL
Input Low Voltage
— V
DDQ
/2 0.43*V
DDQ
V
2, 4, 11,
12
V
IH
Input High Voltage 0.57*V
DDQ
V
DDQ
/2 — V
3, 11,
12
V
IL
Input Low Voltage
(SM_DRAMPWROK)
— — 0.15*V
DDQ
V —
V
IH
Input High Voltage
(SM_DRAMPWROK)
0.45*V
DDQ
— 1.0*V
DDQ
V 10, 13
R
ON_UP(DQ)
LPDDR3 Data Buffer pull-
up Resistance
30 40 50 Ω 5, 12
R
ON_DN(DQ)
LPDDR3 Data Buffer pull-
down Resistance
30 40 50 Ω 5, 12
R
ODT(DQ)
LPDDR3 On-die
termination equivalent
resistance for data signals
150 200 250 Ω 12
V
ODT(DC)
LPDDR3 On-die
termination DC working
point (driver set to receive
mode)
0.45*V
DDQ
0.5*V
DDQ
0.55*V
DDQ
V 12
R
ON_UP(CK)
LPDDR3 Clock Buffer pull-
up Resistance
30 40 50 Ω 5, 12
R
ON_DN(CK)
LPDDR3 Clock Buffer pull-
down Resistance
30 40 50 Ω 5, 12
R
ON_UP(CMD)
LPDDR3 Command Buffer
pull-up Resistance
19 25 31 Ω 5, 12
continued...
Electrical Specifications—Processor
5th Generation Intel
®
Core
™
Processor Family, Intel
®
Core
™
M Processor Family, Mobile Intel
®
Pentium
®
Processor Family, and
Mobile Intel
®
Celeron
®
Processor Family
March 2015 Datasheet – Volume 1 of 2
Order No.: 330834-004v1 91