Datasheet
6 Datasheet, Volume 1
7.7 Signal Groups................................................................................................... 80
7.8 Test Access Port (TAP) Connection ...................................................................... 82
7.9 Storage Conditions Specifications........................................................................ 83
7.10 DC Specifications .............................................................................................. 84
7.10.1 Voltage and Current Specifications ........................................................... 84
7.11 Platform Environmental Control Interface (PECI) DC Specifications .......................... 90
7.11.1 PECI Bus Architecture............................................................................. 90
7.11.2 DC Characteristics ................................................................................. 91
7.11.3 Input Device Hysteresis .......................................................................... 91
8 Processor Land and Signal Information................................................................... 93
8.1 Processor Land Assignments .............................................................................. 93
9 DDR Data Swizzling................................................................................................109
Figures
1-1 Desktop Processor Platform..................................................................................... 10
1-2 Desktop Processor Compatibility Diagram ................................................................. 18
2-1 Intel
®
Flex Memory Technology Operation ................................................................ 26
2-2 PCI Express* Layering Diagram ............................................................................... 28
2-3 Packet Flow Through the Layers............................................................................... 29
2-4 PCI Express* Related Register Structures in the Processor .......................................... 30
2-5 PCI Express* Typical Operation 16 Lanes Mapping ..................................................... 31
2-6 Processor Graphics Controller Unit Block Diagram ...................................................... 33
2-7 Processor Display Block Diagram ............................................................................. 36
4-1 Processor Power States .......................................................................................... 47
4-2 Idle Power Management Breakdown of the Processor Cores ......................................... 51
4-3 Thread and Core C-State Entry and Exit.................................................................... 51
4-4 Package C-State Entry and Exit ............................................................................... 55
7-1 Example for PECI Host-Clients Connection................................................................. 90
7-2 Input Device Hysteresis .......................................................................................... 91
8-1 LGA Socket Land Map............................................................................................. 94
Tables
1-1 Desktop 3rd Generation Intel
®
Core™ Processor Family, Desktop Intel
®
Pentium
®
Processor Family, and Desktop Intel
®
Celeron
®
Processor Family SKUs .......... 16
1-2 Terminology.......................................................................................................... 19
1-3 Related Documents ................................................................................................ 22
2-1 Processor DIMM Support Summary by Product........................................................... 23
2-2 Supported UDIMM Module Configurations.................................................................. 24
2-3 Supported SO-DIMM Module Configurations (AIO Only)............................................... 24
2-4 System Memory Timing Support .............................................................................. 25
2-5 Reference Clock..................................................................................................... 38
4-1 System States....................................................................................................... 48
4-2 Processor Core / Package State Support ................................................................... 48
4-3 Integrated Memory Controller States ........................................................................ 48
4-4 PCI Express* Link States ........................................................................................ 49
4-5 Direct Media Interface (DMI) States ......................................................................... 49
4-6 Processor Graphics Controller States ........................................................................ 49
4-7 G, S, and C State Combinations............................................................................... 49
4-8 Coordination of Thread Power States at the Core Level ............................................... 51
4-9 P_LVLx to MWAIT Conversion .................................................................................. 52
4-10 Coordination of Core Power States at the Package Level.............................................. 54
6-1 Signal Description Buffer Types ............................................................................... 65