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Intel

S5000 Server Board

Family Datasheet

Intel order number D38960-006

Revision 1.3

August 31, 2007

Enterprise Platforms and Services Division

Summary of content (179 pages)

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Intel® S5000 Server Board Family Datasheet Intel order number D38960-006 Revision 1.
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Revision History Intel® S5000 Server Board Family Datasheet Revision History Date 31 May 06 Revision Number 1.1 Modifications 10 Jun 07 1.2 Revised Sections 2.3, 3.13.1, 3.4.1, 3.7; Added Sections 2.4.15, 2.4.15.1; Updated Table 3, 26. Aug 31 07 1.3 Updated Sections 2.2.4, 3.2.1, 3.4.1, 3.4.2.3, 3.7.2.1.8; Updated Table 25 and Figure 17 Initial Document Release. Disclaimers Information in this document is provided in connection with Intel® products.
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Intel® S5000 Server Board Family Datasheet Table of Contents Table of Contents 1. 2. Introduction...........................................................................................................................1 1.1 Server Product References ......................................................................................1 1.2 Chapter Outline ........................................................................................................1 Functional Architecture ..............
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Table of Contents 2.4.16 USB Support ..........................................................................................................21 2.4.17 Native USB Support ...............................................................................................21 2.4.18 Legacy USB Support..............................................................................................21 2.4.19 Super I/O................................................................................................
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Intel® S5000 Server Board Family Datasheet Table of Contents 3.3.8 Memory Modes of Operation..................................................................................38 3.3.9 Memory RAS ..........................................................................................................38 3.3.10 Memory Error Handling ..........................................................................................40 3.4 Platform Control .........................................................
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Table of Contents 3.16 Sleep and Wake Support .....................................................................................105 3.16.1 System Sleep States ............................................................................................105 3.16.2 Wake Events / SCI Sources .................................................................................106 3.17 Non-Maskable Interrupt Handling ........................................................................106 3.
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Intel® S5000 Server Board Family Datasheet 4.8 Table of Contents System Event Log (SEL) ......................................................................................121 4.8.1 Servicing Events ..................................................................................................122 4.8.2 SEL Erasure.........................................................................................................122 4.8.3 Timestamp Clock ....................................................
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Table of Contents Intel® S5000 Server Board Family Datasheet 4.17.3 Critical Interrupt Sensor .......................................................................................134 4.17.4 DIMM Status Sensors ..........................................................................................134 4.17.5 System Memory Redundancy Monitoring ............................................................135 4.17.6 System Memory Monitoring and System Boot ..........................................
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Intel® S5000 Server Board Family Datasheet 5. Table of Contents 4.29.1 IPMI 1.5 Messaging .............................................................................................150 4.29.2 IPMI 2.0 Messaging .............................................................................................151 4.29.3 Intel® 631xESB / 632xESB I/O Controller Hub Embedded LAN Channels ..........152 4.29.4 Address Resolution Protocol Support ..............................................................
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List of Figures Intel® S5000 Server Board Family Datasheet List of Figures Figure 1. Intel® 5000 MCH Functional Architechture.....................................................................3 Figure 2. CEK Processor Mounting.............................................................................................13 Figure 3. FBD Topology ..............................................................................................................15 Figure 4. Identifying Banks of Memory.............
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Intel® S5000 Server Board Family Datasheet List of Tables List of Tables Table 1. DIMM Module Capacities ..............................................................................................16 Table 2. NIC2 Status LED ...........................................................................................................20 Table 3. Supported Processor Configurations ............................................................................25 Table 4. Mixed Processor Configurations ..........
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List of Tables Intel® S5000 Server Board Family Datasheet Table 34. Security Features Operating Model.............................................................................98 Table 35. NMI Error Messages .................................................................................................106 Table 36. Console Redirection Escape Sequences for Headless Operation ............................108 Table 37. BMC Reset Sources and Actions .........................................................
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Intel® S5000 Server Board Family Datasheet 1. Introduction Introduction This datasheet provides information about features and regulatory information that is common to Intel® server boards and Intel® workstation boards that use the Intel® 5000 Series Chipset. This is a companion document to the technical product specifications that are available for each server or workstation board that uses the Intel® 5000 MCH.
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Functional Architecture 2. Intel® S5000 Server Board Family Datasheet Functional Architecture This chapter provides a detailed description of the functionality associated with the architectural blocks that comprise the Intel® 5000 MCH. A diagram of the chipset functional architecture is on the following page. Revision 1.
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Intel® S5000 Server Board Family Datasheet Functional Architecture Figure 1. Intel® 5000 MCH Functional Architechture Revision 1.
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Functional Architecture 2.1 Intel® S5000 Server Board Family Datasheet Intel® 5000 MCH Components The chipsets consist of two components that together are responsible for providing the interface between all major sub-systems found on the Intel® server or workstation board. These subsystems include the processor, memory, and I/O sub-systems.
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Intel® S5000 Server Board Family Datasheet Functional Architecture Intel® 5000 MCH Memory Sub-System Overview 2.1.1.2 The Intel® 5000 MCH provides an integrated memory controller for direct connection to four channels of registered fully-buffered DIMM (FBD) DDR2 533/667 MHz memory (stacked or unstacked). Peak theoretical memory data bandwidth using FBD 533/667 MHz technology is 17 and 21.3 GB/s, respectively. When all four memory channels are populated and operating, they function in lock-step mode.
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Functional Architecture Intel® S5000 Server Board Family Datasheet In the case of a x8 port, the x4 link-pairs first attempt to train independently, and will collapse to a single link at the x8 width upon detection of a single device returning link ID information upstream. Once the number of links has been established, they negotiate to train at the highest common width, and step down in its supported link widths to succeed in training. The result may be that the link has trained as a x1 link.
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Intel® S5000 Server Board Family Datasheet 2.1.1.3.5 Functional Architecture PCI Express* Retrain If the hardware is unable to perform a successful recovery, then the link automatically reverts to the polling state and initiates a full retraining sequence. This is a drastic event with an implicit reset to the downstream device and all subordinate devices, and is logged by the Intel® 5000 MCH as a "Link Down" error.
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Functional Architecture 2.1.2.1 Intel® S5000 Server Board Family Datasheet PCI Interface The Intel® 631xESB / 632xESB I/O Controller Hub PCI interface supports a 33-MHz, Revision 2.3-compliant implementation. All PCI signals are 5-V tolerant, except for PME#. An integrated PCI arbiter supports up to six external PCI bus masters in addition to the internal Intel® 631xESB / 632xESB I/O Controller Hub requests.
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Intel® S5000 Server Board Family Datasheet 2.1.2.5 Functional Architecture Serial ATA (SATA) Host Controller The SATA host controller supports a combination of up to six SATA or four serial attached SCSI (SAS) devices. This provides an interface for SATA hard disks and ATAPI devices. The SATA interface supports PIO IDE transfers up to 16 MB/s and Serial ATA transfers up to 3.0 Gb/s (300 MB/s).
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Functional Architecture 2.1.2.7 Intel® S5000 Server Board Family Datasheet Low Pin Count (LPC) Interface The Intel® 631xESB / 632xESB I/O Controller Hub implements an LPC Interface as described in the Low Pin Count Interface Specification, Revision 1.1. The low pin count (LPC) bridge function of the Intel® 631xESB / 632xESB I/O Controller Hub resides in PCI Device 31: Function 0.
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Intel® S5000 Server Board Family Datasheet 2.1.2.11 Functional Architecture Real-time Clock (RTC) The Intel® 631xESB / 632xESB I/O Controller Hub contains a Motorola* MC146818A-compatible real-time clock with 256 bytes of battery-backed RAM. The real-time clock performs two key functions: keeping track of the time of day and storing system data, even when the system is powered down. The RTC operates on a 32.768-KHz crystal and a separate 3-V lithium battery. The RTC supports two lockable memory ranges.
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Functional Architecture 2.2.1 Intel® S5000 Server Board Family Datasheet Processor Support ® Intel boards that use the Intel® 5000 MCH support one or two Intel® Xeon® 5000 sequence processors that utilize a 667, 1066, or 1333 MHz system bus with frequencies starting at 3.67 GHz. Previous generations of the Intel® Xeon® processors are not supported on these boards. 2.2.2 Processor Population Rules When two processors are installed, both must be of identical revision, core voltage, and bus/core speed.
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Intel® S5000 Server Board Family Datasheet Functional Architecture Heatsink assembly Thermal Interface Material (TIM) Server Board TP02091 CEK Spring Chassis AF000196 Figure 2. CEK Processor Mounting 2.3 Memory Sub-system The Intel® boards that use the Intel® 5000 MCH support several fully-buffered (FBD) memory modes of operation.
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Functional Architecture Intel® S5000 Server Board Family Datasheet memory bandwidth for four FB-DIMM channels. The total bandwidth is based on read bandwidth thus the total bandwidth is 17 GB/s for 533 and 21.0 GB/s for 667. A pair of channels is a branch. Branch 0 consists of channel A and channel B, Branch 1 consists of channel C and channel D. A DIMM can have two ranks; a channel supports a maximum of eight ranks.
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Intel® S5000 Server Board Family Datasheet Functional Architecture Figure 3. FBD Topology 2.3.2 Supported Memory The Intel® 5000 MCH supports single-channel DIMM operation in which only one FBDIMM is installed in DIMM socket A1. Population in other DIMM banks is not supported for singlechannel operation. The server and workstation boards provide the maximum memory capacities outlined in Table 1, based on the number of DIMM slots provided and maximum supported memory loads by the chipset.
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Functional Architecture Intel® S5000 Server Board Family Datasheet Table 1. DIMM Module Capacities SDRAM Parts / SDRAM Technology Used X8, single row 512Mb 512MB 1Gb 1GB 2Gb 2GB 4Gb 4GB X8, double row 1GB 2GB 4GB 8GB X4, single row 512MB 1GB 2GB 4GB X4, Stacked, double row 1GB 2GB 4GB 8GB DIMMs on channel A are paired with DIMMs on channel B to configure 4-way interleaving. Each DIMM pair is referred to as a bank.
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Intel® S5000 Server Board Family Datasheet 2.4 Functional Architecture I/O Sub-system The I/O sub-system consists of several components: PCI sub-system Serial ATA (SATA) support Serial-attached SCSI (SAS) RAID support Parallel ATA (PATA) support Video controller Network interface controller (NIC) USB 2.0 support Super I/O support This section describes the function of each I/O interface and how they operate. 2.4.1 PCI Sub-system 2.4.
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Functional Architecture 2.4.5 Intel® S5000 Server Board Family Datasheet Legacy Option ROM Support The legacy support code in the BIOS will dispatch the legacy option ROMs in the available memory space in the address range 0C0000h-0DFFFFh and will follow all the legacy rules with respect to the option ROM space. If room is available in the E segment, and both C and D segments are already used, the BIOS will also shadow up to 0E7FFF.
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Intel® S5000 Server Board Family Datasheet 2.4.9.1 Functional Architecture Ultra ATA/100 The IDE interface of the Intel® 631xESB / 632xESB I/O Controller Hub ICH DMA protocol redefines signals on the IDE cable to allow both host and target throttling of data and transfer rates of up to 100 MB/s. 2.4.9.2 IDE Initialization The BIOS supports the ATA/ATAPI Specification, version 6.
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Functional Architecture 2.4.11 Intel® S5000 Server Board Family Datasheet SATA RAID Functionality See the server or workstation Technical Product Specification that applies to your product for information. 2.4.12 Serial Attached SCSI See the server or workstation Technical Product Specification that applies to your product for information. 2.4.13 Video Controller See the server or workstation Technical Product Specification that applies to your product for information. 2.4.
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Intel® S5000 Server Board Family Datasheet Functional Architecture provides a secure system power-up, plus the ability to provide BIOS boot options, by sending authenticated IPMI messages directly to the BMC via the onboard NICs. 2.4.16 USB Support The USB controller functionality integrated into the Intel® 631xESB / 632xESB I/O Controller Hub ICH6 provides the server board with the interface for up to eight USB 2.0 ports. One internal USB 2.
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Functional Architecture Intel® S5000 Server Board Family Datasheet Two serial ports Removable media drives Keyboard and mouse support Wake up control System health support 2.4.19.1 General Purpose Input/Output (GPIO) The National Semiconductor* PC87427 Super I/O provides nine general-purpose input/output pins that the server and workstation boards utilize. Note: See the server or workstation Technical Product Specification that applies to your product for information. 2.4.19.
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Intel® S5000 Server Board Family Datasheet 2.5 Functional Architecture Clock Generation and Distribution All buses on the Intel® server and workstation boards that use the Intel® 5000 MCH operate using synchronous clocks. Clock synthesizer/driver circuitry on the server board generates clock frequencies and voltage levels as required, including the following: 200-MHz differential clock at 0.7V logic levels. For processor 1, processor 2, debug port, and the Intel® 5000 MCH.
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System BIOS 3. Intel® S5000 Server Board Family Datasheet System BIOS The BIOS is implemented as firmware that resides in the Flash ROM. It provides hardwarespecific initialization algorithms and standard PC-compatible basic input / output (I/O) services, and standard Intel® Server Board features. The Flash ROM also contains firmware for certain embedded devices. These images are supplied by the device manufacturers and are not specified in this document.
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Intel® S5000 Server Board Family Datasheet System BIOS The BIOS ID is used to identify the BIOS image. It is not used to designate either the board ID or the BIOS phase. The board ID is available in the SMBIOS type 2 structure in which the phase of the BIOS can be determined by the release notes associated with the image. The board ID is also available in BIOS Setup. 3.2 Processors 3.2.
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System BIOS Intel® S5000 Server Board Family Datasheet 45nm 2P Quad-Core Intel® Xeon® Processors* TBD TBD TBD TBD Yes* * Only specific product codes of the Intel ® S5000 server and workstation board family can support the 45nm 2P Dual-Core or 45nm 2P Quad-Core Intel® Xeon® Processors. See the server or workstation Technical Product Specification that applies to your product for more information on dual-core or quad-core processor support.
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Intel® S5000 Server Board Family Datasheet 3.2.6 System BIOS Mixed Processor Cache Sizes If the installed processors have mixed cache sizes, an error is reported to the BMC. The size of all cache levels must match between all installed processors. See Table 4. 3.2.7 Microcode Update If the system BIOS detects a processor for which a microcode update is not available, the BIOS reports an error to the BMC. See Table 4.
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System BIOS Intel® S5000 Server Board Family Datasheet Error Processor frequency (speed) not identical Severity Major System Action The BIOS detects the error condition and responds as follows: Adjusts all processor frequencies to lowest common denominator Continues to boot the system successfully If the frequencies for all processors cannot all be adjusted to be the same, then the BIOS: Logs the error into the SEL Displays “0197: Processor speeds mismatched” message in the error manager Halts
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Intel® S5000 Server Board Family Datasheet System BIOS Detects whether the processor is Intel® Extended Memory 64 Technology (Intel® EM64T) capable Initializes the SMBASE for each processor Detects the appropriate SMRAM State Save Map used by the processor Enables Intel® EM64T during memory initialization if necessary 3.2.13 Execute Disable Bit Feature The Execute Disable Bit feature (XD bit) is an enhancement to the IA-32 Intel® architecture.
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System BIOS Intel® S5000 Server Board Family Datasheet The BIOS will create entries in the multi-processor specification tables to describe dual core processors. 3.2.16 Intel® Virtualization Technology Intel® Virtualization Technology is designed to support multiple software environments sharing the same hardware resources. Each software environment may consist of operating system and applications. The Intel® Virtualization Technology can be enabled or disabled in BIOS Setup.
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Intel® S5000 Server Board Family Datasheet 3.2.17.2 System BIOS Fake MSI Scheme Limitations The following limitations of the Fake MSI Scheme should be understood before using it in a platform: 1. The Fake MSI scheme can only be used by IO devices that support MSI capability (all PCIe devices are required to support either MSI or MSI-X). 2. The Fake MSI scheme cannot be used with a device that supports MSI-X1 (i.e., the device supports MSI-X only and does not support MSI). 3.
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System BIOS 3.3 Intel® S5000 Server Board Family Datasheet Memory The Intel® 5000 MCH supports fully-buffered DIMM (FBDIMM) technology. The integrated Memory Controller Hub in the Intel® 5000 MCH divides the FBDIMMs on the board into two autonomous sets called branches. Each branch has two channels. In dual-channel mode, FBDIMMs on adjacent channels work in lock-step to provide the same cache line data, and a combined ECC. In the single-channel mode, only Channel 0 is active.
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Intel® S5000 Server Board Family Datasheet System BIOS If the Display Logo is disabled, the BIOS displays the total system memory on the diagnostic screen at the end of POST. This total is the same as the amount described by the first bullet, above. The BIOS provides the total amount of memory in the system by supporting the EFI Boot Service function GetMemoryMap(). The BIOS provides the total amount of memory in the system by supporting the INT 15h, E820h function.
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System BIOS Intel® S5000 Server Board Family Datasheet participant ranks, and the process is called Rank Interleaving. The BIOS by default enables 4:1 Rank Interleaving, in which 4 ranks participate in a single cache-line access. 3.3.4 Mixed Speed Memory Modules The BIOS supports memory modules of mixed speed through a combination of user-selected input frequency and the capability of each memory module (FBDIMM).
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Intel® S5000 Server Board Family Datasheet System BIOS The BIOS uses this in-built Memory BIST engine to perform two specific operations: ECC fill to set the memory contents to a known state. This provides a bare minimum error detection capability, and is referred to as the Basic Memory Test algorithm. Extensive FBDIMM testing to search for memory errors on both the memory cells and the data paths. This is referred to as the Comprehensive Memory Test algorithm.
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System BIOS 3.3.7.1 Intel® S5000 Server Board Family Datasheet Memory Sub-system Nomenclature FBDIMMs are organized into physical slots on memory channels that belong to memory branches. Each branch can support a maximum of four DIMM sockets per channel. The memory channels are identified as Channel A, B, C, and D. Channels A and B belong to Branch 0. Channels C and D belong to Branch 1.
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Intel® S5000 Server Board Family Datasheet System BIOS Rule 5: The FBDIMM population of Slot 1 on Branch 0 determines the mode that is selected. If DIMM_A1 and DIMM_B1 cannot lock-step, then the system reverts to singlechannel mode, with DIMM_B1 disabled. Rule 6: As long as Branch 1 cannot satisfy Rules 1 or 2, the Single-channel mode is always given preference over dual-channel mode if the configuration on Slot 1, Branch 0 is not in balance (if DIMM_A1 and DIMM_B1 are not identical.
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System BIOS 3.3.8 Intel® S5000 Server Board Family Datasheet Memory Modes of Operation Based on the available FBDIMM population, the BIOS will configure the system memory into the best possible configuration. Possible configurations in RAS mode are: Single-channel mode Maximum interleave mode (dual-channel mode) Memory mirroring mode DIMM sparing mode (dual or single FBDIMM) Single-channel and dual-channel modes are special cases when RAS is disabled.
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Intel® S5000 Server Board Family Datasheet System BIOS on the feature in BIOS Setup. With sparing enabled, the total effective memory size will be reduced by the size of the spare FBDIMM(s). 3.3.9.2.1 Dual-ranked DIMM Sparing When a dual-ranked FBDIMM is used as a spare, the BIOS has the ability to independently select a physical rank on that FBDIMM as the spare unit and utilize the other physical rank as a normal unit.
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System BIOS Intel® S5000 Server Board Family Datasheet See the server or workstation Technical Product Specification that applies to your product for more information. 3.3.9.4.1 Minimum FBDIMM Population for Mirroring Memory mirroring requires the following minimum requirements: Branch configuration: Mirroring requires both branches to be active.
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Intel® S5000 Server Board Family Datasheet System BIOS Unrecoverable and Fatal Errors: errors that are outside of the scope of the standard ECC engine. These errors are thermal errors, FBD channel errors and data path errors. These errors bring about catastrophic failure of the system.
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System BIOS Intel® S5000 Server Board Family Datasheet The BIOS uses error counters on the Intel® 5000 Series Chipsets and internal software counters to track the number of correctable and Multi-bit correctable errors that occur at runtime. The chipset increments the count for these counters when an error occurs. The count also decays at a given rate, programmable by the BIOS. Because of this particular nature of the counters, they are termed leaky bucket counters.
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Intel® S5000 Server Board Family Datasheet System BIOS successful retry as “Correctable Memory Error” in the SEL regardless of whether the originating error was a CRC error or an ECC error. 3.3.10.1.5 FBD Fatal Error Threshold In addition to standard ECC errors, the BIOS monitors FBD protocol errors reported by the chipset. FBD protocol errors cause degradation of system memory, and hence it is pointless to tolerate them to any level. The BIOS maintains an internal software counter to handle FBD errors.
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System BIOS Intel® S5000 Server Board Family Datasheet 3.3.10.2 Memory Error Reporting Memory errors are reported through a variety of platform-specific elements, as described in this section. Platform Element Event Logging Description When a memory error occurs at runtime, the BIOS will log the error into the system event log in the BMC repository. BIOS Diagnostic / Error Screen At the end of POST, memory errors found during MemBIST are reported in the BIOS Error Manager.
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Intel® S5000 Server Board Family Datasheet 3.3.10.2.2 System BIOS Memory BIST Error Reporting The error manager screen in the BIOS captures memory BIST failures that occurred during the current POST. Table 5. Memory Errors Captured by Error Manager Specific Error Configuration Error Error Class Pause Error Code 0x85F0 Error Text Memory was not configured for the selected memory RAS mode. Description Failure of BIOS to configure the memory system in the selected RAS mode.
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System BIOS Intel® S5000 Server Board Family Datasheet Note: As indicated in the above table, when two FBDIMMs operate in lock-stepped mode. If one of the FBDIMMs fails, the BIOS will also light the DIMM fault LED of the companion FBDIMM. This is because the BIOS cannot isolate failures at the individual FBDIMM level in this mode. In all cases the BMC will light the LEDs after receiving IPMI messages from the BIOS. 3.3.10.2.
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Intel® S5000 Server Board Family Datasheet System BIOS The LEDs are controlled by the BMC, but the BIOS informs the BMC of the memory errors that are described in the table. The methods used to inform the BMC of the error(s) are described section 3.3.10.2.1. It is the responsibility of the BMC to modify the LED behavior according to the notification received from the BIOS. 3.3.10.2.4.
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System BIOS Intel® S5000 Server Board Family Datasheet Table 10. POST Memory Error Handling Scenario POST Message SEL LED State POST Memory BIST Uncorrectable Error (UE) (hard error) Uncorrectable error message that identifies FBDIMM location UE POST code DIMM failed POST code SEL messages identify FBDIMM location DIMM LED: Lit for the failed FBDIMM only. System fault LED: Not lit.
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Intel® S5000 Server Board Family Datasheet System BIOS Table 11. Runtime Memory Error Handling, No Redundancy Scenario POST Message SEL LED State IPMI MEM States Updated System Operation Runtime: Config != RAS Correctable Errors (CE) < Threshold None, because the BIOS does not retain the memory state information across reboots. CE SEL message with DIMM location DIMM fault LED: Not lit. System fault LED: Not lit. No The system continues to operate.
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System BIOS Intel® S5000 Server Board Family Datasheet Table 12. Runtime Error Handling, with Redundancy Scenario POST Message SEL LED State IPMI MEM States Updated No System Operation Runtime: Config = SPARE CE < Threshold None, because the BIOS does not retain the memory state information across reboots. CE SEL message identifying FBDIMM location DIMM fault LED: Not lit. System fault LED: Not lit. The system continues to operate normally.
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Intel® S5000 Server Board Family Datasheet Scenario POST Message Runtime: Config = MIR, and Current State: Redundant UE None, because the BIOS does not retain the memory state information across reboots. System BIOS SEL LED State UE SEL message identifying FBDIMM location DIMM fault LED: Lit for the failed FBDIMM pair. System fault LED: Green / blink IPMI MEM States System Operation Updated The system will NMI.
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System BIOS 3.4 Intel® S5000 Server Board Family Datasheet Platform Control This server platform has embedded platform control which is capable of automatically adjusting system performance and acoustic levels.
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Intel® S5000 Server Board Family Datasheet 3.4.1 System BIOS FBDIMM Open and Closed Loop Thermal Throttling Open-Loop Thermal Throttling (OLTT) Throttling is a solution to cool the DIMMs by reducing memory traffic allowed on the memory bus, which reduces power consumption and thermal output. With OLTT, the system throttles in response to memory bandwidth demands instead of actual memory temperature.
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System BIOS Intel® S5000 Server Board Family Datasheet The BIOS provides data to the BMC telling it which fan profile the platform is setup for, Acoustics Mode or Performance Mode. The BIOS uses the parameters retrieved from the thermal sensor data records (SDR), the fan profile setting from BIOS Setup, and the altitude setting from BIOS Setup to configure the system for memory throttling and fan speed control.
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Intel® S5000 Server Board Family Datasheet Setup Item Throttling Mode Option Open Loop Closed Loop Help Text Open Loop does not rely on a thermal sensor on the board and sets up a static level which equates to a fixed bandwidth. Closed Loop will allow the system to achieve higher performance by monitoring system temps and adjusting bandwidth. Set Fan Profile Performance Acoustic Select the fan control profile that will be used to cool the system.
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System BIOS Intel® S5000 Server Board Family Datasheet additional cooling due to high utilization / power consumption. Memory throttling will be utilized to ensure that the memory thermal limits are not exceeded. 3.5 Flash ROM The BIOS supports the Intel® 28F320C3 flash part. The flash part is a 4 MB flash ROM, 2 MB of which is programmable. The flash ROM contains system initialization routines, setup utility, and runtime support routines. The exact layout is subject to change, as determined by Intel.
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Intel® S5000 Server Board Family Datasheet System BIOS Localization. BIOS Setup uses the Unicode standard and is capable of displaying Setup pages in all languages currently included in the Unicode standard. However, the Intel Server Board BIOS is available only in English. The BIOS Setup utility is functional via console redirection over various terminal emulation standards.
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System BIOS Intel® S5000 Server Board Family Datasheet Table 13. BIOS Setup Page Layout Functional Area Title Bar Description The title bar is located at the top of the screen and displays the title of the form (page) the user is currently viewing. It may also display navigational information. Setup Item List The setup item list is a set of controllable and informational items. Each item in the list occupies the left and center columns in the middle of the screen.
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Intel® S5000 Server Board Family Datasheet System BIOS The keyboard command bar supports the following: Table 14. BIOS Setup: Keyboard Command Bar Key Option Execute Command Description The key is used to activate sub-menus when the selected feature is a submenu, or to display a pick list if a selected option has a value field, or to select a sub-field for multi-valued features like time and date.
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System BIOS 3.7.1.4 Intel® S5000 Server Board Family Datasheet Menu Selection Bar The menu selection bar is located at the top of the screen. It displays the major menu selections. 3.7.2 Server Platform Setup Screens The sections below describe the screens available for the configuration of a server platform. In these sections, tables and figures are used to describe the contents of each screen.
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Intel® S5000 Server Board Family Datasheet System BIOS Figure 6. Setup Utility — Main Screen Display Revision 1.
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System BIOS Intel® S5000 Server Board Family Datasheet Table 15. Setup Utility — Main Screen Fields Setup Item Logged in as Options Help Text Platform ID Comments Information only. Displays password level that setup is running in, Administrator or User. With no passwords set Administrator is the default mode. Information only. Displays the Platform ID. (example: SC5400RA, S5000VSA, or S5000PAL) System BIOS Version Information only. Displays the current BIOS version.
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Intel® S5000 Server Board Family Datasheet System BIOS Setup Item System Time Options [HH:MM:SS] Help Text System Time has configurable fields for Hours, Minutes, and Seconds. Hours are in 24-hour format. Use [Enter] or [Tab] key to select the next field. Use [+] or [-] key to modify the selected field. Setup Item BIOS Version Options No entry allowed BIOS Build Date No entry allowed Information only. Displays the BIOS build date. System ID No entry allowed Information only.
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System BIOS 3.7.2.1 Intel® S5000 Server Board Family Datasheet Advanced Screen The Advanced screen provides an access point to choose to configure several options. On this screen, the user selects the option that is to be configured. Configurations are performed on the selected screen, not directly on the Advanced screen. To access the Advanced screen from the Main screen, press the right arrow until the Advanced screen is chosen. Figure 7. Setup Utility — Advanced Screen Display Revision 1.
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Intel® S5000 Server Board Family Datasheet 3.7.2.1.1 System BIOS Processor Screen The Processor screen provides a place for the user to view the processor core frequency, system bus frequency, and enable or disable several processor options. The user can also select an option to view information about a specific processor. To access this screen from the Main screen select Advanced | Processor. Figure 8. Setup Utility — Processor Configuration Screen Display Table 16.
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System BIOS Setup Item Hyper-Threading Technology Intel® S5000 Server Board Family Datasheet Options Enabled Disabled Help Text Hyper-Threading Technology allows multithreaded software applications to execute threads in parallel within each processor. Comments This option is automatically disabled when Dual Core is disabled. Contact your OS vendor regarding OS support of this feature.
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Intel® S5000 Server Board Family Datasheet Setup Item Processor 1 Information Processor 2 Information Options System BIOS Help Text View Processor 1 information Comments Select to view information about processor 1. This takes the user to a different screen. View Processor 2 information Select to view information about processor 2. This takes the user to a different screen. 3.7.2.1.1.
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System BIOS Intel® S5000 Server Board Family Datasheet Table 17. Setup Utility — Specific Processor Information Screen Fields Setup Item Processor <#> Family Options Help Text Comments Information only. Identifies family or generation of the processor. Maximum Frequency Information only. Maximum frequency the processor core supports. L2 Cache RAM Information only. Size of the processor L2 cache. Processor Stepping Information only. Stepping number of the processor.
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Intel® S5000 Server Board Family Datasheet System BIOS Figure 10. Setup Utility — Memory Configuration Screen Display Table 18. Setup Utility — Memory Configuration Screen Fields Setup Item Total Memory Effective Memory Options Help Text Comments Information only. The amount of memory available in the system in the form of installed FBDIMMs, in units of MB or GB. Information only. The amount of memory available to the operating system in MB or GB.
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System BIOS Setup Item Current Configuration Intel® S5000 Server Board Family Datasheet Options Help Text Comments Information only. Displays one of the following: Maximum Performance Mode: System memory is configured for optimal performance and efficiency and no RAS is enabled. • Single-Channel Mode: System memory is functioning in a special, reduced efficiency mode. Memory Mirroring Mode: System memory is configured for maximum reliability in the form of memory mirroring.
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Intel® S5000 Server Board Family Datasheet 3.7.2.1.2.1 System BIOS Memory RAS and Performance Screen Figure 11. Setup Utility — Memory RAS and Performance Configuration Screen Display Table 19. Setup Utility — Memory RAS and Performance Configuration Screen Fields Setup Item Memory Mirroring Possible Options Yes / No Memory Sparing Possible Yes / No Help Text Comments Information only. Only displayed on systems with chipsets that are capable of Memory Mirroring. Information only Revision 1.
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System BIOS Intel® S5000 Server Board Family Datasheet Setup Item Select Memory RAS Configuration Options RAS Disabled/ Mirroring / Sparing Help Text Available modes depend on the current memory population. [RAS Disabled] - Optimizes system performance. [Mirroring] - Optimizes reliability by using half of physical memory as a backup. [Sparing] - Improves reliability by reserving memory for use as a replacement in the event of DIMM failure. Comments Provides options for configuring Memory RAS.
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Intel® S5000 Server Board Family Datasheet System BIOS Figure 12. Setup Utility — ATA Controller Configuration Screen Display Revision 1.
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System BIOS Intel® S5000 Server Board Family Datasheet Table 20. Setup Utility — ATA Controller Configuration Screen Fields Setup Item Onboard PATA Controller Options Enabled Disabled Help Text Onboard Parallel ATA (PATA) controller. Onboard SATA Controller Enabled Disabled Onboard Serial ATA (SATA) controller. When enabled, the SATA controller can be configured in IDE, RAID, or AHCI Mode. RAID and AHCI modes are mutually exclusive.
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Intel® S5000 Server Board Family Datasheet Setup Item AHCI Mode Options Enabled Disabled System BIOS Help Text Advanced Host Controller Interface (AHCI) option ROM will enumerate all AHCI devices connected to the SATA ports. Contact your OS vendor regarding OS support of this feature. Comments Unavailable if the SATA mode is “Legacy” or if RAID Mode is selected. When AHCI is enabled: The identification and configuration is left to the AHCI Option ROM.
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System BIOS 3.7.2.1.4 Intel® S5000 Server Board Family Datasheet Mass Storage Screen The Mass Storage screen provides fields to configure when a SAS controller is present on the baseboard, mid-plane or backplane of an Intel® system. To access this screen from the Main menu, select Advanced | Mass Storage. Figure 13. Setup Utility — Mass Storage Configuration Screen Display Table 21.
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Intel® S5000 Server Board Family Datasheet Setup Item Intel® RAID Activation Key AXXRAK18E 3.7.2.1.5 Options Present Not Present System BIOS Help Text Comments Information only; Unavailable when Intel® RAID Controller SROMBSAS18E is not present Serial Ports Screen The Serial Ports screen provides fields to configure the Serial A [COM 1] and Serial B [COM2]. To access this screen from the Main screen, select Advanced | Serial Port. Figure 14.
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System BIOS Intel® S5000 Server Board Family Datasheet Table 22. Setup Utility — Serial Ports Configuration Screen Fields Setup Item Options Enabled Disabled Help Text Enable or Disable Serial port A. Address 3F8h 2F8h 3E8h 2E8h Select Serial port A base I/O address. IRQ 3 Select Serial port A base interrupt request (IRQ) line. Serial A Enable 4 Serial B Enabled Disabled Enable or Disable Serial port B. Enable Address 3F8h Select Serial port B base I/O address.
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Intel® S5000 Server Board Family Datasheet System BIOS Figure 15. Setup Utility — USB Controller Configuration Screen Display Table 23. Setup Utility — USB Controller Configuration Screen Fields Setup Item Detected USB Devices USB Controller Options Enabled Disabled Help Text Comments Information only: shows number of USB devices in system [Enabled] - All onboard USB controllers will be turned on and accessible by the OS.
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System BIOS Setup Item Device Reset timeout Options 10 sec Intel® S5000 Server Board Family Datasheet Help Text USB Mass storage device Start Unit command timeout. 20 sec 30 sec 40 sec Header for next line. Storage Emulation One line for each mass storage device in system USB 2.0 controller Comments Auto Floppy Forced FDD Hard Disk CD-ROM [Auto] - USB devices less than 530MB will be emulated as floppy. Enabled Disabled Onboard USB ports will be enabled to support USB 2.0 mode.
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Intel® S5000 Server Board Family Datasheet 3.7.2.1.7 System BIOS PCI Screen The PCI Screen provides fields to configure PCI add-in cards, the onboard NIC controllers, and video options. To access this screen from the Main screen, select Advanced | PCI. Figure 16. Setup Utility — PCI Configuration Screen Display Revision 1.
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System BIOS Intel® S5000 Server Board Family Datasheet Table 24. Setup Utility — PCI Configuration Screen Fields Setup Item Memory Mapped I/O Start Address Options 1.5GB 1.75GB 2.00GB 2.25GB 2.5GB 2.75GB 3.00GB 3.25GB 3.50GB Memory Mapped I/O above 4GB Enabled Onboard Video Enabled Disabled Disabled Help Text Select the start of the reserved memory region for PCI memory mapped I/O space that ends at 4GB.
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Intel® S5000 Server Board Family Datasheet System BIOS To access this screen from the Main screen, select Advanced | System Acoustic and Performance Configuration. Figure 17. Setup Utility — System Acoustic and Performance Configuration Screen Display Revision 1.
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System BIOS Intel® S5000 Server Board Family Datasheet Table 25. Setup Utility — System Acoustic and Performance Configuration Screen Fields Setup Item Throttling Mode Options Open Loop Closed Loop Help Text Open Loop sets up a static level which equates to a fixed bandwidth. It does not rely on a thermal sensor on the board. Closed Loop will allow the system to achieve higher performance by monitoring system temps and adjusting bandwidth.
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Intel® S5000 Server Board Family Datasheet System BIOS Figure 18. Setup Utility — Security Configuration Screen Display Revision 1.
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System BIOS Intel® S5000 Server Board Family Datasheet Table 26. Setup Utility — Security Configuration Screen Fields Setup Item Administrator Password Status Options User Password Status Set Administrator Password [123abcd] Help Text Comments Information only. Indicates the status of administrator password. Information only. Indicates the status of user password. Administrator password is used to control change access in BIOS Setup Utility.
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Intel® S5000 Server Board Family Datasheet 3.7.2.3 System BIOS Server Management Screen The Server Management screen provides fields to configure several server management features. It also provides an access point to the screens for configuring console redirection and displaying system information. To access this screen from the Main screen, select the Server Management option. Figure 19. Setup Utility — Server Management Configuration Screen Display Table 27.
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System BIOS Intel® S5000 Server Board Family Datasheet Setup Item Options Resume on AC Power Stay Off Loss Last state Reset Help Text System action to take on AC power loss recovery. [Stay Off] - System stays off. [Last State] - System returns to the same state before the AC power loss. [Reset] - System powers on. Clear System Event Log Clears the System Event Log. All current entries will be lost. Enabled Disabled Comments Note: This option will be reset to [Disabled] after a reboot.
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Intel® S5000 Server Board Family Datasheet System BIOS Figure 20. Setup Utility — Console Redirection Screen Display Table 28. Setup Utility — Console Redirection Configuration Fields Setup Item Console Redirection Options Disabled Serial A Serial B Help Text Console redirection allows a serial port to be used for server management tasks. [Disabled] - No console redirection. [Serial Port A] - Configure serial port A for console redirection.
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System BIOS Setup Item Baud Rate Intel® S5000 Server Board Family Datasheet Options 9600 19.2K 38.4K 57.6K Help Text Serial port transmission speed. Setting must match the remote terminal application. Comments 115.2K Terminal Type PC-ANSI VT100 VT100+ VT-UTF8 Legacy OS Redirection 3.7.2.4 Disabled Enabled Character formatting used for console redirection. Setting must match the remote terminal application. This option will enable legacy OS redirection (i.e., DOS) on serial port.
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Intel® S5000 Server Board Family Datasheet System BIOS Table 29.
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System BIOS Intel® S5000 Server Board Family Datasheet Figure 22. Setup Utility — Setup Utility – Boot Options Screen Display Revision 1.
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Intel® S5000 Server Board Family Datasheet System BIOS Table 30. Setup Utility — Setup Utility – Boot Options Screen Display Setup Item Boot Timeout Options 0 - 65535 Help Text The number of seconds BIOS will pause at the end of POST to allow the user to press the [F2] key for entering the BIOS Setup Utility. Valid values are 0-65535. Zero is the default. A value of 65535 will cause the system to go to the Boot Manager menu and wait for user input for every system boot.
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System BIOS Intel® S5000 Server Board Family Datasheet Figure 23. Setup Utility — Setup Utility – Boot Manager Screen Display Table 31. Setup Utility — Setup Utility – Boot Manager Screen Display Setup Item Launch EFI Shell Options Help Text Select this option to boot now. Comments Note: This list is not the system boot option order. Use the Boot Options menu to view and configure the system boot option order. Boot Device #x Select this option to boot now.
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Intel® S5000 Server Board Family Datasheet 3.7.2.7 System BIOS Error Manager Screen The Error Manager screen displays any errors encountered during POST. Figure 24. Setup Utility — Error Manager Screen Display Table 32. Setup Utility — Error Manager Screen Fields Setup Item Option s Help Text Displays System Errors 3.7.2.8 Comments Information only. Displays errors that occurred during this POST.
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System BIOS Intel® S5000 Server Board Family Datasheet Figure 25. Setup Utility — Exit Screen Display Table 33. Setup Utility — Exit Screen Fields Setup Item Save Changes and Exit Help Text Exit BIOS Setup Utility after saving changes. The system will reboot if required. The [F10] key can also be used. Comments User is prompted for confirmation only if any of the setup fields were modified. Discard Changes and Exit Exit BIOS Setup Utility without saving changes. The [Esc] key can also be used.
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Intel® S5000 Server Board Family Datasheet Setup Item Save as User Default Values Help Text Save current BIOS Setup Utility values as custom user default values. If needed, the user default values can be restored via the Load User Default Values option below. System BIOS Comments User is prompted for confirmation. Note: Clearing CMOS or NVRAM will cause the user default values to be reset to the factory default values. Load User Default Values 3.8 Load user default values.
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System BIOS Intel® S5000 Server Board Family Datasheet Table 34. Security Features Operating Model Mode Password on boot Entry Method / Event Power On / Reset Entry Criteria Behavior User password set and password on boot enabled in BIOS Setup. Secure boot disabled in BIOS Setup. System halts for user password before scanning option ROMs. The system is not in secure mode. No mouse or keyboard input is accepted except the password. 3.9.2 Password Protection Exit Criteria User password.
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Intel® S5000 Server Board Family Datasheet System BIOS Boot to the ROM-DOS shell and copy IFlash32.exe and the BIOS binary file (also referred as capsule file) to a DOS bootable diskette, CD or disk-on-key. 3.10.1.
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System BIOS [–h|?] Intel® S5000 Server Board Family Datasheet Displays command line help information. Syntax examples: flashupdt –u ftp://ftp.examplesite.com/UpdatePackage/ServerName flashupdt –u "ftp://ftp.examplesite.com/Update Package/Server Name" flashupdt –u ftp://Kevin:87w09@ftp.examplesite.com/UpdatePackage/ServerName For Windows*: flashupdt –u c:\UpdatePackage\ServerName For Linux: flashupdt –u /UpdatePackage/ServerName 3.10.2.
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Intel® S5000 Server Board Family Datasheet 3.10.2.3.2 System BIOS Linux To remove the Intel® One Boot Flash Update utility from a Linux operating system, do the following: 1. Log in as root. 2. Open a terminal and change the working directory to the Intel® One Boot Flash Update utility installation directory: cd /usr/local/flashupdt 3. Execute the following command: /uninstall 3.
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System BIOS Intel® S5000 Server Board Family Datasheet successful, the BIOS update is complete. If the new BIOS fails to boot successfully, a timer is started and the system rolls back to the previous, healthy BIOS image. 1. Boot the system with the jumper covering pins 2 and 3. 2. Update the BIOS using iFlash32.exe or the Intel® One Flash Update (Intel® One Boot Flash Update utility) utility. 3. Reset the system. 4. The current BIOS will validate and then boot from the new BIOS. 5.
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Intel® S5000 Server Board Family Datasheet System BIOS manually added by the user through the Boot Maintenance Manager of the Setup utility. The Boot Maintenance Manager provides the capability to make permanent changes to the boot order. It is also possible to change the first boot option for a single boot. 3.13.
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System BIOS Intel® S5000 Server Board Family Datasheet This product supports the Hardware Design Guide for Microsoft Windows 2000 Server, Version 3.0 enterprise requirements. 3.14.2 Advanced Configuration and Power Interface (ACPI) The primary role of the ACPI BIOS is to supply the ACPI tables. POST creates the ACPI tables and locates them in extended memory (above 1 MB). The location of these tables is conveyed to the ACPI-aware operating system through a series of tables located throughout memory.
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Intel® S5000 Server Board Family Datasheet System BIOS Power Button — Off to On The BMC monitors the power button and the wake up event signals from the chipset. A transition from either source results in the BMC starting the power-up sequence. Since the processors are not executing, the BIOS does not participate in this sequence. The hardware receives the power good and reset signals from the BMC and then transitions to an on state.
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System BIOS 3.16.2 Intel® S5000 Server Board Family Datasheet Wake Events / SCI Sources The server or workstation board supports the following wake-up sources in the ACPI environment. The operating system controls enabling and disabling these wake sources: Devices that are connected to any USB port, such as USB mice and keyboards, can wake the system from the S1 and S3 sleep states. The serial port can be configured to wake the system from the S1 sleep state.
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Intel® S5000 Server Board Family Datasheet System BIOS The BIOS enables the system interface to the BMC in early POST. The BIOS logs system events and POST error codes during the system operation. The BIOS logs a boot event to BMC early in POST. The events logged by the BIOS follow the Intelligent Platform Management Interface Specification, Version 2.0. 3.20 Console Redirection The BIOS supports redirection of both video and keyboard via a serial link (serial port).
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System BIOS Intel® S5000 Server Board Family Datasheet Table 36. Console Redirection Escape Sequences for Headless Operation Escape Sequence RrR This will implement but will default to “disabled”. 3.20.3 Description Remote Console Reset Limitations BIOS Console redirection terminates after an EFI-aware operating system calls EFI Exit Boot Services. The operating system is responsible for continuing console redirection after that. BIOS console redirection is a text console.
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Intel® S5000 Server Board Family Datasheet System BIOS The use of serial port console redirection allows a single serial cable to be used for each server system. The serial cables from a number of servers can be connected to a serial concentrator or to a switch. This allows access to each individual server system. The system administrator can remotely switch from one server to another to manage large numbers of servers.
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System BIOS Intel® S5000 Server Board Family Datasheet administrator can obtain the types, capabilities, operational status, installation date and other information about the server components. Revision 1.
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Intel® S5000 Server Board Family Datasheet 4. System Management 4.1 Feature Support System Management This section provides a high-level list of management features supported by the Intel® 631xESB / 632xESB I/O Controller Hub BMC. 4.1.1 Legacy Features These features are carried over from previous platforms with little or no change in functionality. 4.1.1.1 IPMI 2.0 Features See the IPMI 2.0 Specification for more information on the features listed in this section.
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System Management Intel® S5000 Server Board Family Datasheet Serial Over LAN (SOL) ACPI state synchronization – The BMC tracks ACPI state changes (provided by BIOS). BMC self test – The BMC performs initialization and run-time self tests and makes results available to external entities. 4.1.1.2 Non-IPMI Features This section lists non-IPMI feature support carried over from prior generation of servers. PSMI 1.
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Intel® S5000 Server Board Family Datasheet 4.1.2 System Management New Features This section lists features that are being introduced on server boards that use the Intel® 5000 Series Chipsets. Acoustic management – Improved acoustic levels are achieved by including support for fan profiles using TControl ver2 SDRs. BMC timeclock sync with SIO RTC – At BMC startup, the BMC reads SIO RTC and updates its internal timeclock to match.
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System Management Intel® S5000 Server Board Family Datasheet The following is a simplified block diagram showing the power and reset signal interconnections to the Intel® 631xESB / 632xESB I/O Controller Hub. Figure 26. Intel® 631xESB / 632xESB I/O Controller Hub Power / Reset Signals Revision 1.
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Intel® S5000 Server Board Family Datasheet 4.3 System Management BMC Reset Control The following table shows the sources of BMC resets, and the actions by the server and the BMC as a result. Table 37. BMC Reset Sources and Actions 4.3.1 Reset Source Standby power comes up System Reset? No (system is not up yet) BMC Reset Yes BMC exits firmware update mode No Yes BMC Exits Firmware Update Mode The BMC firmware can be updated using firmware transfer commands through the LPC interface.
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System Management 4.4.1.3 Intel® S5000 Server Board Family Datasheet Watchdog Timer Timeout Reason Bits To implement FRB2, during POST the BIOS determines whether a BMC watchdog timer timeout occurred on the previous boot attempt. If it finds a watchdog timeout did occur, it determines whether that timeout was an FRB2 timeout, system management software (SMS) timeout, or an intentional, timed hard reset. 4.4.1.
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Intel® S5000 Server Board Family Datasheet 4.5 System Management Integrated Front Panel User Interface The BMC incorporates the front panel interface functionality and supports an SSI EB compliant model. Indicators on supported front panels are LEDs. 4.5.1 Power LED The green power LED is active when system DC power is on. The power LED is controlled by the BIOS. The power LED reflects a combination of the state of system (DC) power and the system ACPI state.
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System Management Intel® S5000 Server Board Family Datasheet The following table maps the platform state to the LED state. Table 39. System Status LED Indicator States Color Off Green / Amber State N/A Alternating Blink Criticality Not ready Not ready Description AC power off Pre DC power on – 15-20 second BMC initialization when AC power is applied to the server. The control panel buttons are disabled until the BMC initialization is complete. System booted and ready.
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Intel® S5000 Server Board Family Datasheet 4.5.3 System Management Chassis ID LED The chassis ID LED provides a visual indication of a system being serviced. It is toggled by the chassis ID button Table 40. Chassis ID LED Indicator States 4.5.4 State Identify active via button LED State Solid on Off Off Front Panel / Chassis Inputs The BMC monitors the front panel buttons and other chassis signals.
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System Management 4.5.4.3 Intel® S5000 Server Board Family Datasheet Reset Button An assertion of the front panel reset signal to the BMC causes the system to start the reset and reboot process, as long as the BMC has not locked-out this input. This assertion is immediate and without the cooperation from software or the operating system. The reset button is a momentary contact button on the front panel. Its signal is routed through the front panel connector to the BMC, which monitors and de-bounces it.
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Intel® S5000 Server Board Family Datasheet System Management Front panel lock-out allows specific front panel buttons to be protected. This protection includes blocking the buttons and generating violation events if one of the buttons is pressed while the front panel is in a lock-out state. Support is available only for protecting the front panel power and reset buttons as a unit. These buttons cannot be individually locked.
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System Management 4.8.1 Intel® S5000 Server Board Family Datasheet Servicing Events Events can be received while the SEL is being cleared. The BMC implements an event message queue to avoid the loss of messages. Queued messages are not overwritten. The BMC recognizes duplicate event messages by comparing sequence numbers and the message source. For more information, see the IPMI 2.0 Specification.
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Intel® S5000 Server Board Family Datasheet 4.9 System Management Sensor Data Record (SDR) Repository The BMC implements the logical sensor data record (SDR) repository as specified in the Intelligent Platform Management Interface Specification, Version 2.0 The SDR repository is accessible via all communication transports. This way, out-of-band interfaces can access SDR repository information while the system is down. The BMC allocates 65,536 bytes (64 KB) of non-volatile storage space for the SDR. 4.9.
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System Management Intel® S5000 Server Board Family Datasheet 4.11 Diagnostics and Beep Code Generation The BMC can generate beep codes upon detection of failure conditions. Beep codes are sounded each time the problem is discovered, such as on each power-up attempt, but are not sounded continuously. Codes that are common across all platforms that use one of the Intel® 5000 Series Chipsets are listed in the following table.
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Intel® S5000 Server Board Family Datasheet 4.12.1 System Management Signal Generation The BMC generates an NMI pulse under certain conditions. The BMC-generated NMI pulse duration is at least 30 ms. After an NMI has been generated by the BMC, the BMC will not generate another until the system has been reset or powered down. BMC NMI generation can be disabled in the system BIOS. The following will cause the BMC to generate an NMI pulse: The front panel diagnostic interrupt button has been pressed.
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System Management 4.13.1 Intel® S5000 Server Board Family Datasheet Processor Status Sensors The BMC provides IPMI sensor of type Processor for monitoring various status information for each processor slot supported by the platform. With the exception of the processor presence offset, if an event state (sensor offset) has been asserted, it will remain asserted until one of the following occurrences: The processor retest option is enabled in BIOS setup. A/C power cycle occurs.
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Intel® S5000 Server Board Family Datasheet 4.13.3 System Management ThermTrip Monitoring The BMC is responsible for persistently retaining ThermTrip history for each processor. This history tracks whether the processor has had a ThermTrip since the last processor sensor rearm or retest. When a thermal trip occurs, the BMC will poll the ThermTrip status for each processor. If the BMC has detected that a ThermTrip occurred, then it will set the ThermTrip offset for the applicable processor status sensor.
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System Management Intel® S5000 Server Board Family Datasheet processor increases in temperature, the amount of time the processor spends in a throttled state will increase, until 100% throttling is reached. 4.13.5.1.1 IPMI Sensor Support for PROCHOT PROCHOT time window: The PROCHOT sensor measures the % of throttling on an individual processor over a 5.8 second time window. Detecting PROCHOT sensors: The PROCHOT sensors will be a type code (01h) = temperature, but is read as a %.
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Intel® S5000 Server Board Family Datasheet 4.13.9 System Management Processor Thermal Control Monitoring (Prochot) The BMC monitors processor thermal control monitoring for each processor. This functionality is provided by the National Semiconductor* LM94 system management controller device, which provides a reading of the percentage of time that the processor ProcHot signal is asserted over a given measurement window. The BMC implements this as a threshold sensor on a perprocessor basis. 4.13.
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System Management Intel® S5000 Server Board Family Datasheet Boost: The associated fan in a critical or non-recoverable state in a non-redundant fan configuration. The fan domain is a state of insufficient resources in a redundant fan configuration. Any temperature sensor in a critical or non-recoverable state, with the exception of Processor Thermal Control Monitoring sensor (Prochot) or VRD Over-Temperature (VRDHot) sensors.
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Intel® S5000 Server Board Family Datasheet System Management than or equal to the current reading of the temperature sensor. The corresponding fan speed is used as the domain fan contribution of that sub-record. Hysteresis is applied to the difference calculated from the previously used reading to the current reading. If the difference is positive, the temperature is increasing and the specified positive hysteresis is subtracted.
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System Management 4.14.4 Intel® S5000 Server Board Family Datasheet Sleep State Fan Control Using the Set ACPI Configuration Mode command, the BMC may be configured to set the fans to a fixed sleep state speed when the system is in the S1 sleep state. 4.14.5 Fan Redundancy Detection The BMC supports redundant fan monitoring and implements fan redundancy sensors.
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Intel® S5000 Server Board Family Datasheet System Management 4.16 PSMI Support Platforms that use the Intel® 5000 Series Chipsets support PSMI v1.44 compliant power supplies. Some power supplies may not support certain optional features, such as current monitoring. 4.17 System Memory RAS and Bus Error Monitoring System memory and bus error monitoring is done by the system BIOS. At startup, the BIOS checks the chipset for any memory errors early in the boot process.
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System Management 4.17.3 Intel® S5000 Server Board Family Datasheet Critical Interrupt Sensor The BMC implements a Critical Interrupt (13h) sensor for reporting the following conditions / events: Bus Uncorrectable Error: Only sensed after an SMI timeout (post-mortem) Front Panel NMI / diagnostic interrupt: Monitored during normal system operation 4.17.4 DIMM Status Sensors There is one DIMM status sensor per DIMM slot.
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Intel® S5000 Server Board Family Datasheet 4.17.4.5 System Management Deassertion of Offsets The BMC will de-assert (reset) the DIMM fault and / or disabled state for the following reasons: The BMC receives the Set DIMM State command instructing it to de-assert either or both of these states. A DIMM slot becomes empty A ReArm Sensor command is executed for that DIMM sensor A ReArm DIMMs command is executed. DIMM grouping 4.17.4.
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System Management 4.17.5.1 Intel® S5000 Server Board Family Datasheet DIMM Sparing With DIMM sparing, the BMC will implement two sensors per DIMM sparing domain (the set of DIMMs which share a spare set of DIMMs). Each sparing domain will have an associated unique Entity ID. Both sensors will belong to that Entity. DIMM sparing redundancy sensor Sparing redundancy is determined by the BIOS. The BIOS conveys this state to the BMC.
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Intel® S5000 Server Board Family Datasheet System Management Memory mirroring redundancy sensor Memory mirroring redundancy is determined by the BIOS. The BIOS conveys this state to the BMC. The BMC then sets the state of the associated sensor for the specific mirroring domain appropriately. This sensor is of type Availability Status (0Bh) and indicates whether the domain is redundant or not (i.e., whether all mirrored DIMM(s) are available for use).
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System Management 4.17.6 Intel® S5000 Server Board Family Datasheet System Memory Monitoring and System Boot The following sequence of events describes the system booting process with respect to the system memory monitoring feature. During system boot, BIOS will determine the DIMM population and set this state in the BMC. The BMC initializes the DIMM sensor state based on the discovered presence information and persistent fault information.
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Intel® S5000 Server Board Family Datasheet System Management 4.19 Field Replaceable Unit (FRU) / Fault LED Control Several sets of FRU / POST / fault LEDs are supported. Some LEDs are owned by the BMC and some by the BIOS. The BMC owns control of the following FRU / fault LEDs: Fan fault LEDs: There is a fan fault LED associated with each fan. The BMC will light a fan fault LED if the associated fan tach sensor has a lower critical threshold event status asserted.
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System Management Intel® S5000 Server Board Family Datasheet The BMC provides configuration command interfaces when used with an Intel® RMM. This is done through a combination of IPMI and IPMI OEM commands. The BMC does not automatically handle this configuration. It relies on the Intel® RMM to discover the BMC add-in support and then to configure the BMC according to the Intel® RMM requirements. Typically, the Intel® RMM would have been previously configured by a software utility. 4.21.
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Intel® S5000 Server Board Family Datasheet 4.21.3.1 System Management SEL Forwarding When BMC SEL events are generated through any mechanism other than the Add SEL Entry command, the BMC will send time-stamped copies of these events to the Intel® RMM). Events are forwarded even if the BMC’s SEL is full. 4.21.3.2 BMC Status Change Forwarding The BMC sends notifications of other status change events that may be of interest to the registered add-in device.
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System Management Intel® S5000 Server Board Family Datasheet These specifications are defined in the following sub-sections. Section 4.26 talks about basic characteristics of the communication protocols used in all of the above interfaces. 4.22 Channel Management Every messaging interface is assigned an IPMI channel ID by IPMI 2.0. Commands are provided to configure each channel for privilege levels and access modes. The following table shows the standard channel assignments: Table 45.
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Intel® S5000 Server Board Family Datasheet System Management 4.26 Host to BMC Communication Interface 4.26.1 LPC / KCS Interface The BMC has three 8042 keyboard controller style (KCS) interface ports as described in the IPMI 2.0 specification. These interfaces are mapped into the host I/O space and accessed via the chipset low pin count (LPC) bus. These interfaces are assigned with the following uses and addresses: Table 46.
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System Management Intel® S5000 Server Board Family Datasheet 4.27 IPMB Communication Interface The IPMB is a communication protocol that utilizes the 100 KB/s version of an I2C bus as its physical medium. For more information on I2C specifications, see The I2C Bus and How to Use It. The IPMB implementation in the BMC is compliant with the IPMB v1.0, revision 1.0. The BMC both sends and receives IPMB messages over the IPMB interface. Non-IPMB messages received via the IPMB interface are discarded.
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Intel® S5000 Server Board Family Datasheet 4.27.3 System Management IPMB LUN Routing The BMC can receive either request or response IPMB messages. The treatment of these messages depends on the destination logical unit number (LUN) in the IPMB message. For IPMB request messages, the destination LUN is the responder’s LUN. For IPMB response messages, the destination LUN is the requester’s LUN. The disposition of these messages is described in the following table. The BMC accepts LUN 00b and LUN 10b.
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System Management Intel® S5000 Server Board Family Datasheet Figure 8 shows a logical block diagram of the BMC receiving IPMB messages. IPMB I2C INTERFACE IPMB MSG VERIFICATION LUN ROUTING LUN=00b (BMC) LUN=10b (SMS) RECEIVE MSG QUEUE SMS_ATN Flag BMC IPMB MSG Handler Other BMC Commands Get Msg Cmd SMS Interface Event Message Buffer SMM_ATN Flag SEL DEVICE Read Event Msg SMM Interface Figure 28. BMC IPMB Message Reception Revision 1.
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Intel® S5000 Server Board Family Datasheet System Management 4.28 Emergency Management Port (EMP) Interface The EMP interface is the Intel implementation of the IPMI 2.0 IPMI over serial feature. The primary goal of providing an out-of-band RS232 connection is to give system administrators the ability to access low-level server management firmware functions by using commonly available tools.
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System Management Intel® S5000 Server Board Family Datasheet 4.28.3.1 Input Restrictions 4.28.3.1.1 Maximum Input Length The BMC supports a maximum of 122 characters per line. The BMC will stop accepting new characters and stop echoing input when the 122-character limit is reached. However, selected characters will continue to be accepted and handled appropriately even after the character limit is reached. These are the , / , illegal, and input characters. 4.28.3.1.
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Intel® S5000 Server Board Family Datasheet 4.28.3.2.2 System Management Text Command Privilege Levels The BMC supports the privilege level scheme for terminal mode text commands as specified in Table 48. 4.28.3.3 Bridging Support The BMC supports the optional bridging functionality described in the IPMI 2.0 specification. 4.28.
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System Management Intel® S5000 Server Board Family Datasheet 4.29 LAN Interface The BMC implements both the IPMI 1.5 and IPMI 2.0 messaging models. These provide out-ofband local area network (LAN) communication between the BMC and the external world. The BMC supports a maximum of three LAN interfaces: Two of the LAN interfaces utilize the embedded Intel® 631xESB / 632xESB I/O Controller Hub NICs (one channel per embedded NIC).
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Intel® S5000 Server Board Family Datasheet 4.29.2 System Management IPMI 2.0 Messaging IPMI 2.0 messaging is built over RMCP+ and has a different session establishment protocol. The session commands are defined by RSSP and implemented at the RMCP+ level, not IPMI commands. Authentication is implemented at the RMCP+ level. RMCP+ provides link payload encryption, so it is possible to communicate private / sensitive data (confidentiality). The BMC supports the following cipher suites: Table 49.
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System Management 4.29.3 Intel® S5000 Server Board Family Datasheet Intel® 631xESB / 632xESB I/O Controller Hub Embedded LAN Channels ® Even though the Intel 631xESB / 632xESB I/O Controller Hub embedded NICs are shared by the BMC and the server, sharing means only that both the BMC and the server use the same NIC. These shared NICs provide a dedicated MAC address solely for BMC use. As a result, in some ways these channels are more similar to a dedicated LAN channel than a shared channel.
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Intel® S5000 Server Board Family Datasheet 5. Error Reporting and Handling Error Reporting and Handling This chapter provides error message, error codes, and beep codes. For information about the role of the BIOS in error handling and the interaction between the BIOS, platform hardware, and server management firmware with regard to error handling see Chapter 4, System Management. 5.
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Error Reporting and Handling 5.2 Intel® S5000 Server Board Family Datasheet Error Handling and Logging This section defines how errors are handled by the system BIOS, including a discussion of the role of the BIOS in error handling and the interaction between the BIOS, platform hardware, and server management firmware with regard to error handling. In addition, error-logging techniques are described and beep codes for errors are defined. 5.2.
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Intel® S5000 Server Board Family Datasheet 5.2.2.3 Error Reporting and Handling Processor Bus Error The BIOS enables the error correction and detection capabilities of the processors by setting appropriate bits in the processor model specific register (MSR) and the appropriate bits in the chipset. In the case of unrecoverable errors on the host processor bus, proper execution of the SMI handler cannot be guaranteed and the handler cannot be relied upon to log such conditions.
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Error Reporting and Handling 5.3 Intel® S5000 Server Board Family Datasheet Error Messages and Error Codes The system BIOS displays error messages on the screen. Before video initialization, beep codes inform the user of errors. POST error codes are logged in the event log. The BIOS displays POST error codes on the screen. 5.3.1 Diagnostic LEDs During the system boot process, the BIOS executes several platform configuration processes, each of which is assigned a specific hex POST code number.
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Intel® S5000 Server Board Family Datasheet Error Reporting and Handling A. Status LED D. Bit 1 LED (POST LED) B. ID LED E. Bit 2 LED (POST LED) C. MSB LED (POST LED) F. LSB LED (POST LED) Figure 29. Location of Diagnostic LEDs on Server Board Note: See the server or workstation Technical Product Specification that applies to your product for more detailed information on the location of the back panel diagnostic LEDs. 5.3.2 POST Code Checkpoints Table 52.
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Error Reporting and Handling Intel® S5000 Server Board Family Datasheet 0x53h Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB Bit 1 Bit 2 LSB Off R G A Reserved for PCI bus 0x54h Off A Off R Reserved for PCI bus 0x55h Off A Off A Reserved for PCI bus 0x56h Off A G R Reserved for PCI bus 0x57h Off A G A Reserved for PCI bus Checkpoint Description USB 0x58h G R Off R Resetting USB bus 0x59h G R Off A Reserved for USB devices ATA / ATAPI / SATA 0x5Ah G R G R R
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Intel® S5000 Server Board Family Datasheet 0xBAh Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB Bit 1 Bit 2 LSB A Off A R 0xBCh A Checkpoint G R R Error Reporting and Handling Description Detecting presence of a removable media device (IDE CDROM detection, etc.
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Error Reporting and Handling Intel® S5000 Server Board Family Datasheet Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB Bit 1 Bit 2 LSB Pre-EFI Initialization Module (PEIM) / Recovery Description Checkpoint 0x30h Off Off R R Crisis recovery has been initiated because of a user request 0x31h Off Off R A Crisis recovery has been initiated by software (corrupt flash) 0x34h Off G R R Loading crisis recovery capsule 0x35h Off G R A Handing off control to the crisis recovery capsule
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Intel® S5000 Server Board Family Datasheet Error Reporting and Handling Error Code 8161 Error Message Processor 02 unable to apply BIOS update Response Pause 8190 Watchdog timer failed on last boot Pause 8198 Operating system boot watchdog timer expired on last boot Pause 0192 L3 cache size mismatch Halt 0194 CPUID, processor family are different Halt 0195 Front side bus mismatch Pause 0197 Processor speeds mismatched Pause 8300 Baseboard management controller failed self-test Pause
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Error Reporting and Handling Intel® S5000 Server Board Family Datasheet Error Code 858C Error Message DIMM_D1 Correctable ECC error encountered. Response Pause 858D DIMM_D2 Correctable ECC error encountered. Pause 858E DIMM_D3 Correctable ECC error encountered. Pause 858F DIMM_D4 Correctable ECC error encountered. Pause 8600 Primary and secondary BIOS IDs do not match.
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Intel® S5000 Server Board Family Datasheet Glossary Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (e.g., “82460GX”) with alpha entries following (e.g., “ACPI”). Acronyms are then entered in their respective place, with non-acronyms following. Term ACPI Definition Advanced Configuration and Power Interface ADC Analog to Digital Converter. AP Application Processor API Application Programming Interface.
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Glossary Intel® S5000 Server Board Family Datasheet Term ICMB Intelligent Chassis Management Bus Definition IERR Internal Error IFB I/O and Firmware Bridge INTR Interrupt IP Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface IR Infrared ITP In-Target Probe KB 1024 bytes KCS Keyboard Controller Style LAN Local Area Network LCD Liquid Crystal Display LED Light Emitting Diode LPC Low Pin Count LUN Logical Unit Number MAC
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Intel® S5000 Server Board Family Datasheet Glossary Term 5000 The chipset used in the server board.
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Reference Documents Intel® S5000 Server Board Family Datasheet Reference Documents See the following documents for additional information: Advanced Configuration and Power Interface Specification, Revision 1.0b. 1996, 1997, 1998. Intel Corporation, Microsoft Corporation, Toshiba Corporation. Design for Test R18. BIOS/Firmware. Intel Corporation. I2C Address Allocation, Revision 1.13. 1997. Intel Corporation. Intelligent Platform Management Interface Specification, Version 1.5. 2000.
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Intel® S5000 Server Board Family Datasheet Reference Documents PCI Power Management Specification, Revision 1.0, http://www.pcisig.org/ PCI IRQ Routing Table Specification, Revision 1.0, Microsoft Corporation. POST Memory Manager Specification, Revision 1.01, http://www.phoenix.com/NR/rdonlyres/873A00CF-33AC-4775-B77E08E7B9754993/0/specspmm101.pdf Plug and Play BIOS Specification, Revision 1.0a, http://www.microsoft.com/whdc/system/pnppwr/pnp/default.