Datasheet

Intel® S5000 Server Board Family Datasheet System Management
Revision 1.3
Intel order number D38960-006
135
4.17.4.5 Deassertion of Offsets
The BMC will de-assert (reset) the DIMM fault and / or disabled state for the following reasons:
 The BMC receives the Set DIMM State command instructing it to de-assert either or both
of these states.
 A DIMM slot becomes empty
 A ReArm Sensor command is executed for that DIMM sensor
 A ReArm DIMMs command is executed.
 DIMM grouping
4.17.4.6 DIMM Grouping
The following table provides the grouping of FBDIMMs.
Figure 27. DIMM Grouping
DIMM Sensor Sensor
Number
DIMM 1A EOh
DIMM 2A E1h
DIMM 1B E2h
DIMM 2B E3h
DIMM 1C E4h
DIMM 2C E5h
DIMM 1D E6h
DIMM 2D E7h
4.17.5 System Memory Redundancy Monitoring
The Intel
®
5000 Series Chipsets support memory redundancy features that go beyond single bit
error correction, allowing failing or failed DIMMs to be managed on-line without affecting normal
system operation. BMC support for these is indicated in the following sections.
Note: See the server or workstation Technical Product Specification that applies to your product
for more information.