Datasheet

Functional Architecture Intel® S5000 Server Board Family Datasheet

Revision 1.3

Intel order number D38960-006

memory bandwidth for four FB-DIMM channels. The total bandwidth is based on read bandwidth

thus the total bandwidth is 17 GB/s for 533 and 21.0 GB/s for 66

A pair of channels is a branch. Branch 0 consists of channel A and channel B, Branch 1

consists of channel C and channel D. A DIMM can have two ranks; a channel supports a

maximum of eight ranks.

In non-mirrored operation, the two DDR2 channels within a branch operate in lock-step and the

branches operate independently. When memory mirroring is configured, the channels operate in

lock-step under normal conditions, but independently under failure and recovery conditions.

The Intel

5000 MCH supports a burst length of four in either single-channel mode or dual-

channel mode. In dual-channel mode this results in eight 64-bit chunks (64-byte cache line)

from a single read or write. In single-channel mode, two reads or writes are required to access a

cache line of data.

Memory between 32 GB, and 32 GB minus 512 MB, is not accessible for use by the operating

system and may be lost to the user. This area is reserved for the BIOS, APIC configuration

space, PCI adapter interface, and virtual video memory space. This means that if 32 GB of

memory is installed, 31.5 GB of this memory is usable. The chipset should allow the remapping

of unused memory above the 32 GB address, but this memory may not be accessible to an

operating system that has a 32 GB memory limit.

To boot the system, the system BIOS uses a dedicated I

C bus to retrieve DIMM information

needed to program the Intel

5000 MCH memory registers.

2.3.1 Fully-buffered DIMM (FBDIMM)

The fully-buffered DIMM (FBDIMM) memory interface provides a high-bandwidth, large-capacity

channel solution that has a narrow host interface. FBDIMMs use commodity DRAMs isolated

from the channel behind an advanced memory buffer (AMB) on the DIMM that allows a greater

number of devices per channel without loading the interconnect and affecting performance.

Memory capacity remains at a maximum of 36 devices per DIMM and total memory capacity

scales with DRAM bit density.

FBD is a differential pair, point-to-point interface. The interface consists primarily of 10

southbound differential pairs (outputs from the Intel

5000 MCH to the DIMMs) and 14

northbound differential pairs (inputs to the Intel

5000 MCH from the DIMMs). The Intel

5000

MCH is connected only to the closest FBDIMM in the channel and communicates with the AMB

on that FBDIMM. The AMB on the closest FBDIMM communicates with the AMB on the next

FBDIMM in the channel, and so on. This point-to-point solution eliminates problems associated

with a “stub-bus” architecture and allows memory capacity to increase without loading the

channel. The figure below shows the FBD topology.