Datasheet

Intel® S5000 Server Board Family Datasheet System BIOS

Revision 1.3

Intel order number D38960-006

3.2.17.2 Fake MSI Scheme Limitations

The following limitations of the Fake MSI Scheme should be understood before using it in a

platform:

1. The Fake MSI scheme can only be used by IO devices that support MSI capability (all

PCIe devices are required to support either MSI or MSI-X).

2. The Fake MSI scheme cannot be used with a device that supports MSI-X

(i.e., the

device supports MSI-X only and does not support MSI).

3. The Fake MSI scheme can be used with MSI capable devices only. It cannot be used

with a device that only supports MSI-X.

4. The I/OxAPIC interrupt used for Fake MSI cannot be shared. This is because MSI is an

edge triggered mechanism and sharing will result in loss of interrupts.

5. Even if the IO device is multiple message capable, firmware must program the device to

allocate one vector only (the Fake MSI scheme cannot support MSI multiple messages).

This is required in order to ensure that the device-function does not modify any bits of

the message data field.

6. Each IO device that intends to use the Fake MSI scheme should be programmed to a

unique MSI data value corresponding to a unique I/OxAPIC input. The MSI address

remains the same as we are targeting the PAR of the ESB2 I/OxAPIC.

7. If the IO device generates interrupts for multiple internal events, the device driver ISR

must check for all internal events on each interrupt

. Otherwise, overrun situations are

possible.

8. In case of multi-function devices, the Fake MSI scheme can be used to support up to 4

functions only. This is because interrupt routing of devices using the Fake MSI scheme

are exposed to the operating system using MPS1.4 or _PRT table; these firmware tables

are limited to 4 unique interrupts per device as required by the PCI Specification.

3.2.18 Acoustical Fan Speed Control

The processors implement a methodology for managing processor temperatures that supports

acoustic noise reduction through fan speed control. There are two components to the

temperature calculation used to regulate the fans: T

CONTROL offset and TCONTROL base. The

BIOS retrieves the T

CONTROL offset from a processor MSR and sends it to the BMC. The BMC

is responsible for getting the T

CONTROL base from the sensor data records and adding it to the

value received from the BIOS.

MSI-X requires BAR registers to be initialized to locate the MSI-X table in MMIO space. Since legacy operating

systems could potentially reconfigure the device and its BARs, in the case of “Fake MSI”, there is a risk of losing the

MSI-X programming done by the BIOS.

The concern here is that a device driver written with level triggered semantics in mind may dismiss the interrupt with

processing all the internal events associated with the interrupt because it is assured that the interrupt will be

reasserted as long as internal events are pending.