Intel® Celeron® Processor up to 1.10 GHz Datasheet ■ ■ ■ ■ ■ ■ ■ Available at 1.10 GHz, 1 GHz, 950 MHz, 900 MHz, 850 MHz, 800 MHz, 766 MHz, 733 MHz, 700 MHz, 667 MHz, 633 MHz, 600 MHz, 566 MHz, 533 MHz, 533A MHz, 500 MHz, 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, and 300A MHz core frequencies with 128 KB level-two cache (on die); 300 MHz and 266 MHz core frequencies without level-two cache. Intel’s latest Celeron® processors in the FC-PGA/FC-PGA2 package are manufactured using the advanced 0.
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Intel® Celeron® Processor up to 1.10 GHz Contents 1.0 Introduction.......................................................................................................................11 1.1 1.2 2.0 Electrical Specifications....................................................................................................15 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 3.0 System Bus and Vref...........................................................................................
Intel® Celeron® Processor up to 1.10 GHz 3.4.5 3.5 4.0 Thermal Specifications and Design Considerations......................................................... 65 4.1 5.0 5.2 5.3 5.4 5.5 6.2 6.3 Mechanical Specifications for the Boxed Intel® Celeron® Processor ................ 110 6.1.1 Mechanical Specifications for the S.E.P. Package............................... 110 6.1.1.1 Boxed Processor Heatsink Weight.......................................... 112 6.1.1.
Intel® Celeron® Processor up to 1.10 GHz Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Datasheet Clock Control State Machine...............................................................................16 BCLK to Core Logic Offset ..................................................................................48 BCLK*, PICCLK, and TCK Generic Clock Waveform .........................................49 System Bus Valid Delay Timings ....
Intel® Celeron® Processor up to 1.10 GHz 39 40 41 42 43 44 6 Side View Airspace Requirements for the Boxed Intel® Celeron® Processor in the FC-PGA/FC-PGA2 and PPGA Packages .............................. 116 Volumetric Keepout Requirements for The Boxed Fan Heatsink...................... 116 Clip Keepout Requirements for the 370-Pin (Top View) ................................... 117 Boxed Processor Fan Heatsink Power Cable Connector Description ..............
Intel® Celeron® Processor up to 1.10 GHz Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Datasheet Processor Identification .......................................................................................13 Voltage Identification Definition ...........................................................................20 Intel® Celeron® Processor System Bus Signal Groups.......................................22 Absolute Maximum Ratings........................
Intel® Celeron® Processor up to 1.10 GHz 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 8 AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor Pins (For FC-PGA/FC-PGA2 Packages) ........................................... 55 AGTL+ Signal Groups Ringback Tolerance Guidelines for Edge Finger Measurement on the S.E.P. Package .................................................................
Intel® Celeron® Processor up to 1.10 GHz Revision History Datasheet Revision Date -020 January 2002 Description • Added IHS specifications for 900 MHz, 950 MHz, and 1 GHz. • Added 566 MHz specification for CPUID of 068Ah.
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Intel® Celeron® Processor up to 1.10 GHz 1.0 Introduction The Intel® Celeron® processor is based on the P6 microarchitecture and is optimized for the Value PC market segment. The Intel Celeron processor, like the Pentium ® II processor, features a Dynamic Execution microarchitecture and executes MMX™ technology instructions for enhanced media and communication performance.
Intel® Celeron® Processor up to 1.10 GHz 1.1.1 Package Terminology The following terms are used often in this document and are explained here for clarification: • Processor substrate—The structure on which passive components (resistors and capacitors) are mounted. • Processor core—The processor’s execution engine. • S.E.P. Package—Single-Edge Processor Package, which consists of a processor substrate, processor core, and passive components. This package differs from the S.E.C.
Intel® Celeron® Processor up to 1.10 GHz 1.1.2 Processor Naming Convention A letter(s) is added to certain processors (e.g., 533A MHz) when the core frequency alone may not uniquely identify the processor. Below is a summary of what each letter means as well as a table listing all the FC-PGA/FC-PGA2 processors for the PGA370 socket. Table 1.
Intel® Celeron® Processor up to 1.10 GHz 1.
Intel® Celeron® Processor up to 1.10 GHz 2.0 Electrical Specifications 2.1 System Bus and VREF Celeron processor signals use a variation of the low voltage Gunning Transceiver Logic (GTL) signaling technology. The Intel Celeron processor system bus specification is similar to the GTL specification, but has been enhanced to provide larger noise margins and reduced ringing. The improvements are accomplished by increasing the termination voltage level and controlling the edge rates.
Intel® Celeron® Processor up to 1.10 GHz 2.2.1 Normal State—State 1 This is the normal operating state for the processor. 2.2.2 AutoHALT Power Down State—State 2 AutoHALT is a low power state entered when the processor executes the HALT instruction. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself.
Intel® Celeron® Processor up to 1.10 GHz 2.2.3 Stop-Grant State—State 3 The Stop-Grant state on the processor is entered when the STPCLK# signal is asserted. Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to VTT) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the system bus should be driven to the inactive state.
Intel® Celeron® Processor up to 1.10 GHz While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep state, by stopping the BCLK input. (See Section 2.2.6.) Once in the Sleep state, the SLP# pin can be deasserted if another asynchronous system bus event occurs. The SLP# pin has a minimum assertion of one BCLK period. 2.2.6 Deep Sleep State—State 6 The Deep Sleep state is the lowest power state the processor can enter while maintaining context.
Intel® Celeron® Processor up to 1.10 GHz The PPGA package has more power (88) and ground (80) pins than the S.E.P. Package. Of the power pins, 77 are used for the processor core (VCCCORE) and 8 are used as a AGTL+ reference voltage (VREF). The other 3 power pins are VCC1.5, VCC2.5 and VCCCMOS and are used for future processor compatibility. FC-PGA/FC-PGA2 packages have 77 VCCCORE, 77 ground pins, eight VREF, one VCC1.5, one VCC2.5, and one VCCCMOS.
Intel® Celeron® Processor up to 1.10 GHz 2.5 Voltage Identification The processor’s voltage identification (VID) pins can be used to automatically select the VCCCORE voltage from a compatible voltage regulator. There are five VID pins (VID[4:0]) on the S.E.P. Package, while there are only four (VID[3:0]) on the PGA packages. This is because there are no Celeron processors in the PGA package that require more than 2.05 V (see Table 2).
Intel® Celeron® Processor up to 1.10 GHz 2.6 System Bus Unused Pins All RESERVED pins must remain unconnected. Connection of these pins to VCCCORE, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future Celeron processor products. See Section 5.0 for a pin listing of the processor and the location of each RESERVED pin. For Intel Celeron processors in the S.E.P.
Intel® Celeron® Processor up to 1.10 GHz open drain and should be pulled high to VCCCMOS. This ensures not only correct operation for current Intel Celeron processors, but compatibility for future Intel Celeron processor products as well. The groups and the signals contained within each group are shown in Table 3. Refer to Section 7.0 for descriptions of these signals. Table 3.
Intel® Celeron® Processor up to 1.10 GHz 2.7.1 Asynchronous Vs. Synchronous for System Bus Signals All AGTL+ signals are synchronous to BCLK. All of the CMOS, APIC, and TAP signals can be applied asynchronously to BCLK. All APIC signals are synchronous to PICCLK. All TAP signals are synchronous to TCK. 2.7.2 System Bus Frequency Select Signal (BSEL[1:0]) The BSEL pins have two functions.
Intel® Celeron® Processor up to 1.10 GHz Table 4. Absolute Maximum Ratings Symbol TSTORAGE Parameter Min Max Unit –40 85 °C • PPGA and S.E.P.P. –0.5 Operating voltage + 1.0 V • FC-PGA/FC-PGA2 –0.5 2.1 V • PPGA and S.E.P.P. –0.3 VCCCORE + 0.7 V • FC-PGA/FC-PGA2 VTT - 2.18 2.18 V 7, 8 • PPGA and S.E.P.P. -0.3 3.3 V 3 • FC-PGA/FC-PGA2 VTT - 2.18 -0.58 2.18 3.
Intel® Celeron® Processor up to 1.10 GHz Table 5. Voltage and Current Specifications (Sheet 1 of 5) Processor Symbol Parameter Min Core Freq Notes 2.00 2, 3, 4 2.00 2, 3, 4 0650h 2.00 2, 3, 4 0651h 2.00 2, 3, 4 0660h 2.00 2, 3, 4 0665h 2.00 2, 3, 4 0660h 2.00 2, 3, 4 0665h 2.00 2, 3, 4 0660h 2.00 2, 3, 4 0665h 2.00 2, 3, 4 0660h 2.00 2, 3, 4 0665h 2.00 2, 3, 4 0660h 2.00 2, 3, 4 0665h 2.00 2, 3, 4 466 MHz 0665h 2.00 2, 3, 4 500 MHz 0665h 2.
Intel® Celeron® Processor up to 1.10 GHz Table 5. Voltage and Current Specifications (Sheet 2 of 5) Processor Symbol Parameter Min Core Freq 800 MHz 850 MHz 900 MHz VCCCORE VCC for processor core 1 GHz 1.10 GHz Notes 1.65 2, 3, 20 1.70 2, 3, 20 068Ah 1.75 2, 3, 20 — — 0686h 1.70 2, 3, 20 068Ah 1.75 2, 3, 20 — — — — 068Ah 1.75 — — — — — — V 2, 3, 20 — — — — 068Ah 1.75 2, 3, 20 — — — — — — 068Ah 1.75 2, 3, 20 — — — — — — 068Ah 1.
Intel® Celeron® Processor up to 1.10 GHz Table 5. Voltage and Current Specifications (Sheet 3 of 5) Processor Symbol Parameter Min Typ Max Unit — –0.140 — 0.140 V 7 — — -0.144 — 0.144 V 8 — — -0.130 — — -0.110 266 MHz — 8.2 300 MHz — 9.3 9, 10 300A MHz — 9.3 9, 10 333 MHz — 10.
Intel® Celeron® Processor up to 1.10 GHz Table 5. Voltage and Current Specifications (Sheet 4 of 5) Processor Symbol Parameter Min Core Freq Typ 266 MHz 1.12 300 MHz 1.15 300A MHz 1.15 333 MHz 1.18 366 MHz 1.21 400 MHz 1.25 433 MHz 1.30 466 MHz 1.35 500 MHz 1.43 533 MHz 1.52 533A MHz ISGNT 28 ICC Stop-Grant for processor core Max 566 MHz 600 MHz Unit Notes CPUID 2.5 — — — 6.921 6.921 633 MHz 6.921 667 MHz 6.921 700 MHz 6.921 733 MHz 6.921 766 MHz 6.
Intel® Celeron® Processor up to 1.10 GHz Table 5. Voltage and Current Specifications (Sheet 5 of 5) Processor Symbol Parameter Min Core Freq Typ 266 MHz ISLP ICC Sleep for processor core Max 0.94 300A MHz 0.94 333 MHz 0.96 366 MHz 0.97 400 MHz 0.99 433 MHz 1.01 466 MHz 1.03 500 MHz 1.09 533 MHz 1.16 533A MHz 2.5 600 MHz Notes 0.90 300 MHz 566 MHz Unit CPUID — — — 6.622 6.922 633 MHz 6.922 667 MHz 6.922 700 MHz 6.922 733 MHz 6.922 766 MHz 6.922 800 MHz 6.
Intel® Celeron® Processor up to 1.10 GHz NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VCCCORE and ICCCORE supply the processor core. 3. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. 4. Use the Typical Voltage specification with the Tolerance specifications to provide correct voltage regulation to the processor. 5. VTT must be held to 1.5 V ± 9%.
Intel® Celeron® Processor up to 1.10 GHz Table 6. AGTL+ Signal Groups DC Specifications Symbol Parameter Min Max Unit Notes • S.E.P.P and PPGA –0.3 0.82 V • FC-PGA/FC-PGA2 –0.150 VREF – 0.200 V 9 • S.E.P.P and PPGA 1.22 VTT V 2, 3 • FC-PGA/FC-PGA2 VREF + 0.200 VTT V 2, 3 Input Low Voltage VIL Input High Voltage VIH RON Buffer On Resistance 16.67 Ω 8 IL Leakage Current for inputs, outputs, and I/O ±100 µA 6, 7 NOTES: 1.
Intel® Celeron® Processor up to 1.10 GHz Table 7. Non-AGTL+ Signal Group DC Specifications Symbol Parameter Min Max Unit Notes VIL Input Low Voltage –0.3 0.7 V 10 VIH Input High Voltage 1.7 2.625 V 2.5 V +5% maximum, Note 10 VIL1.5 Input Low Voltage –0.150 VREF - 0.200 V 8, 9 VIL2.5 Input Low Voltage -0.58 0.700 V 7, 9 VIH1.5 Input High Voltage VREF + 0.200 VTT V 5, 8, 9 VIH2.5 Input High Voltage 2.0 3.18 V 7, 9 VOL Output Low Voltage 0.4 V 2 2.
Intel® Celeron® Processor up to 1.10 GHz 2.11 AGTL+ System Bus Specifications It is recommended that the AGTL+ bus be routed in a daisy-chain fashion with termination resistors to VTT at each end of the signal trace. These termination resistors are placed electrically between the ends of the signal traces and the VTT voltage supply and generally are chosen to approximate the substrate impedance. The valid high and low levels are determined by the input buffers using a reference voltage called VREF.
Intel® Celeron® Processor up to 1.10 GHz 2.12 System Bus AC Specifications The Celeron processor system bus timings specified in this section are defined at the Intel Celeron processor edge fingers and the processor core pins. Timings specified at the processor edge fingers only apply to the S.E.P. Package and timings given at the processor core pins apply to all S.E.P. Package and PGA packages. Unless otherwise specified, timings are tested at the processor core during manufacturing.
Intel® Celeron® Processor up to 1.10 GHz Table 9. System Bus AC Specifications (Clock) at the Processor Edge Fingers (for S.E.P. Package) T# Parameter Min System Bus Frequency T1’: BCLK Period Nom Max 66.67 0.78 T2’: BCLK Period Stability Figure Notes MHz 15.0 T1B’: SC242 to Core Logic BCLK Offset Unit ± 300 ns 3 4, 5, 6 ns 3 Absolute Value 7,8 ps See Table 10 T3’: BCLK High Time 4.44 ns 3 @>2.0 V 6 T4’: BCLK Low Time 4.44 ns 3 @<0.5 V 6 T5’: BCLK Rise Time 0.84 2.
Intel® Celeron® Processor up to 1.10 GHz Table 10. System Bus AC Specifications (Clock) at the Processor Core Pins (for Both S.E.P. and PGA Packages) T# Parameter Min System Bus Frequency T1: BCLK Period Nom Max 66.67 Figure Notes MHz 15.0 T2: BCLK Period Stability Unit ± 300 ns 3 4, 5, 6 ps 3 6, 8, 9 T3: BCLK High Time 4.94 ns 3 @>2.0 V 6 T4: BCLK Low Time 4.94 ns 3 @<0.5 V 6 T5: BCLK Rise Time • S.E.P.P. and PPGA 0.34 1.36 ns 3 (0.5 V–2.0 V) 6, 10 • FC-PGA/FC-PGA2 0.
Intel® Celeron® Processor up to 1.10 GHz Table 11. System Bus AC Specifications (SET Clock)1, 2 T# Parameter Min T4: BCLK Low Time Unit Figure MHz 100.00 10.0 ns 10.0 ±250 T2: BCLK Period Stability T3: BCLK High Time Max 66.67 System Bus Frequency T1: BCLK Period Nom ±250 2.5 2.5 2.4 2.4 Notes 4 3 4, 5, 10 4, 5, 11 6, 7, 10 ps 6, 7, 11 ns 3 ns 3 9, 10 9, 11 9, 10 9, 11 T5: BCLK Rise Time 0.4 1.6 ns 3 3, 8 T6: BCLK Fall Time 0.4 1.6 ns 3 3, 8 NOTES: 1.
Intel® Celeron® Processor up to 1.10 GHz Table 12. Valid Intel® Celeron® Processor System Bus, Core Frequency Core Frequency (MHz) BCLK Frequency (MHz) Frequency Multiplier 266 66 4 300 66 4.5 333 66 5 366 66 5.5 400 66 6 433 66 6.5 466 66 7 500 66 7.5 533 66 8 566 66 8.5 600 66 9 633 66 9.5 667 66 10 700 66 10.5 733 66 11 766 66 11.5 800 100 8 850 100 8.5 900 100 9 950 100 9.5 1,000 100 10 1,100 100 11 NOTES: 1.
Intel® Celeron® Processor up to 1.10 GHz Table 13. System Bus AC Specifications (AGTL+ Signal Group) at the Processor Edge Fingers (for S.E.P. Package) T# Parameter Min Max Unit Figure Notes T7’: AGTL+ Output Valid Delay 1.07 6.37 ns 4 4, 5 T8’: AGTL+ Input Setup Time 1.96 ns 5 4, 6, 7, 8 T9’: AGTL+ Input Hold Time 1.53 ns 5 4, 9 T10’: RESET# Pulse Width 1.00 ms 6 10 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies. 2.
Intel® Celeron® Processor up to 1.10 GHz Table 15. Processor System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins (for PPGA Package) T# Parameter Min Max Unit Figure Notes T7: AGTL+ Output Valid Delay 0.30 4.43 ns 4 5 T8: AGTL+ Input Setup Time 2.10 ns 5 5, 6, 7 T9: AGTL+ Input Hold Time 0.85 ns 5 T10: RESET# Pulse Width 1.00 ms 6 7, 8 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2.
Intel® Celeron® Processor up to 1.10 GHz Table 17. System Bus AC Specifications (CMOS Signal Group) at the Processor Edge Fingers (for S.E.P. Package) T# Parameter Min Max Unit Figure Notes T14’: CMOS Input Pulse Width, except PWRGOOD 2 BCLKs 8 Active and Inactive states T14B: LINT[1:0] Input Pulse Width 6 BCLKs 8 5 T15’: PWRGOOD Inactive Pulse Width 10 BCLKs 8 6, 7 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies. 2.
Intel® Celeron® Processor up to 1.10 GHz Table 19. System Bus AC Specifications (CMOS Signal Group) 1, 2, 3, 4 T# Parameter Min Max Unit Figure T14: CMOS Input Pulse Width, except PWRGOOD 2 BCLKs 4 T15: PWRGOOD Inactive Pulse Width 10 BCLKs 4, 8 Notes Active and Inactive states 5 NOTES: 1. Unless otherwise noted, all specifications in this table apply to Celeron processors at all frequencies 2. These specifications are tested during manufacturing. 3.
Intel® Celeron® Processor up to 1.10 GHz 44 Table 22. System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Edge Fingers (for S.E.P. Package) T# Parameter Min Max Unit Figure T21’: PICCLK Frequency 2.0 33.3 MHz T22’: PICCLK Period 30.0 500.0 ns 3 T23’: PICCLK High Time 12.0 ns 3 Notes T24’: PICCLK Low Time 12.0 ns 3 T25’: PICCLK Rise Time 0.25 3.0 ns 3 T26’: PICCLK Fall Time 0.25 3.0 ns 3 T27’: PICD[1:0] Setup Time 8.
Intel® Celeron® Processor up to 1.10 GHz Table 23. System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Core Pins (For S.E.P. and PGA Packages) T# Parameter Min Max Unit Figure T21: PICCLK Frequency 2.0 33.3 MHz T22: PICCLK Period 30.0 500.0 ns 3 Notes T23: PICCLK High Time • S.E.P.P and PPGA 11.0 ns 3 @>2.0 V • FC-PGA/FC-PGA2 10.5 ns 3 @>1.7 V • S.E.P.P and PPGA 11.0 ns 3 @<0.5 V • FC-PGA/FC-PGA2 10.5 ns 3 @<0.7 V T25: PICCLK Rise Time 0.25 3.
Intel® Celeron® Processor up to 1.10 GHz Table 24. System Bus AC Specifications (APIC Clock and APIC I/O)1, 2, 3 T# Parameter Min Max Unit MHz T21: PICCLK Frequency 2.0 33.3 T22: PICCLK Period 30.0 500.0 T23: PICCLK High Time 10.5 T24: PICCLK Low Time 10.5 T25: PICCLK Rise Time 0.25 3.0 T26: PICCLK Fall Time 0.25 3.0 T27: PICD[1:0] Setup Time 5.0 Figure Notes ns 3 ns 3 ns 3 @ < 0.7 V ns 3 (0.7 V–1.7 V) ns 3 (1.7 V–0.7 V) ns 5 4 @ > 1.7 V T28: PICD[1:0] Hold Time 2.
Intel® Celeron® Processor up to 1.10 GHz Table 26. System Bus AC Specifications (TAP Connection) at the Processor Core Pins (for Both S.E.P. and PPGA Packages) T# Parameter Min T30: TCK Frequency Max Unit 16.667 MHz Figure Notes T31: TCK Period 60.0 ns 3 T32: TCK High Time 25.0 ns 3 @1.7 V; 10 T33: TCK Low Time 25.0 ns 3 @0.7 V; 10 T34: TCK Rise Time 5.0 ns 3 (0.7 V–1.7 V); 4, 10 T35: TCK Fall Time 5.0 ns 3 (1.7 V–0.
Intel® Celeron® Processor up to 1.10 GHz Table 27. System Bus AC Specifications (TAP Connection)1, 2, 3 T# Parameter Min T30: TCK Frequency Max Unit 16.667 MHz Figure Notes T31: TCK Period 60.0 ns 3 T32: TCK High Time 25.0 ns 3 VREF + 0.200 V, 10 T33: TCK Low Time 25.0 ns 3 VREF – 0.200 V, 10 ns 3 (VREF – 0.200 V) – (VREF + 0.200 V), T34: TCK Rise Time 5.0 4, 10 T35: TCK Fall Time 5.0 ns 3 (VREF + 0.200 V) – (VREF – 0.200 V), 4, 10 T36: TRST# Pulse Width 40.
Intel® Celeron® Processor up to 1.10 GHz Note: For Figure 3 through Figure 10, the following apply: 1. Figure 3 through Figure 10 are to be used in conjunction with Table 9 through Table 26. 2. All AC timings for the AGTL+ signals at the processor edge fingers are referenced to the BCLK rising edge at 0.50 V. This reference is to account for trace length and capacitance on the processor substrate, allowing the processor core to receive the signal with a reference at 1.25 V.
Intel® Celeron® Processor up to 1.10 GHz Figure 3. BCLK*, PICCLK, and TCK Generic Clock Waveform th tr 1.7V (2.0V*) 1.25V CLK 0.7V (0.5V*) tf tl tp Tr Tf Th Tl Tp = = = = = T5, T6, T3, T4, T1, T25, T26, T23, T24, T22, T34 T35 T32 T33 T31 (Rise Tim e) (Fall Tim e) (High Tim e) (Low Time) (BLCK, TCK, PICCLK Period) Note: BCLK is referenced to 0.5 V and 2.0 V. PICCLK is referenced to 0.7 V and 1.7 V. For S.E.P. and PPGA packages, TCK is referenced to 0.7 V and 1.7 V.
Intel® Celeron® Processor up to 1.10 GHz Figure 6. System Bus Reset and Configuration Timings (For the S.E.P. and PPGA Packages) BCLK Tu Tt RESET# Tv Tw Configuration (A[14:5]#, BR0#, FLUSH#, INT#) Tx Valid Tt Tu Tv Tw Tx = T9 (AGTL+ Input Hold Time) = T8 (AGTL+ Input Setup Time) = T10 (RESET# Pulse Width) = T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time) = T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time) Figure 7.
Intel® Celeron® Processor up to 1.10 GHz Figure 8. Power-On Reset and Configuration Timings BCLK VccCORE, VTT, VREF PWRGOOD VIL, max Ta VIH, min Tb RESET# TC Configuration (A20M#, IGNNE#, INTR, NMI) Valid Ratio Ta Tb Tc = T15 (PWRGOOD Inactive Pulse) = T10 (RESET# Pulse Width) = T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time) (FC-PGA) Figure 9. Test Timings (TAP Connection) 1.25V TCK Tv Tw Tr Ts 1.
Intel® Celeron® Processor up to 1.10 GHz 3.0 System Bus Signal Simulations Signals driven on the Celeron processor system bus should meet signal quality specifications to ensure that the components read data properly and to ensure that incoming signals do not affect the long term reliability of the component. Specifications are provided for simulation at the processor core; guidelines are provided for correlation to the processor edge fingers.
Intel® Celeron® Processor up to 1.10 GHz Table 29. BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins (for the FC-PGA/FC-PGA2 Packages) T# Parameter Min Max Unit Figure V1: BCLK VIL 0.50 V 11 V1: PICCLK VIL 0.70 V 11 V 11 V2: BCLK VIH Nom 2.00 V2: PICCLK VIH 2.00 V3: VIN Absolute Voltage Range –0.58 V4: BCLK Rising Edge Ringback V4: PICCLK Rising Edge Ringback Notes V 11 V 11 2.00 V 11 2 2.00 V 11 2 3.18 V5: BCLK Falling Edge Ringback 0.
Intel® Celeron® Processor up to 1.10 GHz Table 30. BCLK Signal Quality Guidelines for Edge Finger Measurement (for the S.E.P. Package) T# Parameter Min Nom V1’: BCLK VIL V2’: BCLK VIH 2.0 V3’: VIN Absolute Voltage Range –0.5 V4’: Rising Edge Ringback 2.0 Unit Figure 0.5 V 12 V 12 V 12 2 3.3 V5’: Falling Edge Ringback V6’: Tline Ledge Voltage Max 1.0 V7’: Tline Ledge Oscillation Notes V 12 3 0.5 V 12 3 1.7 V 12 At Ledge Midpoint 4 0.2 V 12 Peak-to-Peak 5 NOTES: 1.
Intel® Celeron® Processor up to 1.10 GHz 3.2 AGTL+ Signal Quality Specifications and Measurement Guidelines Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which are available in AP-585, Pentium® II Processor AGTL+ Guidelines (Order Number 243330). Refer to the Pentium® II Processor Developer's Manual (Order Number 243502) for the AGTL+ buffer specification. Table 31 provides the AGTL+ signal quality specifications (for both the S.E.P.
Intel® Celeron® Processor up to 1.10 GHz Table 33. AGTL+ Signal Groups Ringback Tolerance Guidelines for Edge Finger Measurement on the S.E.P. Package T# Parameter Min Unit Figure Notes α’: Overshoot 100 mV 13 τ’: Minimum Time at High 1.5 ns 13 4 ρ ’: Amplitude of Ringback –250 mV 13 4, 5 φ’: Final Settling Voltage 250 mV 13 4 δ’: Duration of Squarewave Ringback N/A ns 13 NOTES: 1. Unless otherwise noted, all guidelines in this table apply to all Celeron processor frequencies.
Intel® Celeron® Processor up to 1.10 GHz 3.3 Non-AGTL+ Signal Quality Specifications and Measurement Guidelines There are three signal quality parameters defined for non-AGTL+ signals: overshoot/undershoot, ringback, and settling limit. All three signal quality parameters are shown in Figure 14 for the nonAGTL+ signal group. Figure 14.
Intel® Celeron® Processor up to 1.10 GHz 3.3.2 Ringback Specification Ringback refers to the amount of reflection seen after a signal has switched. The ringback specification is the voltage that the signal rings back to after achieving its maximum absolute value. (See Figure 14 for an illustration of ringback.) Excessive ringback can cause false signal detection or extend the propagation delay. The ringback specification applies to the input pin of each receiving agent.
Intel® Celeron® Processor up to 1.10 GHz 3.3.3 Settling Limit Guideline Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach before its next transition. The amount allowed is 10 percent of the total signal swing (VHI – VLO) above and below its final value. A signal should be within the settling limits of its final value, when either in its high state or low state, before it transitions again.
Intel® Celeron® Processor up to 1.10 GHz After the true waveform conversion, the undershoot/overshoot specifications shown in Table 38 and Table 39 can be applied to the converted undershoot waveform using the same magnitude and pulse duration specifications used with an overshoot waveform. Overshoot/undershoot magnitude levels must observe the Absolute Maximum Specifications listed in Table 38 and Table 39. These specifications must not be violated at any time regardless of bus activity or system state.
Intel® Celeron® Processor up to 1.10 GHz 3.4.5 Reading Overshoot/Undershoot Specification Tables (FC-PGA/ FC-PGA2 Packages) The overshoot/undershoot specification for the FC-PGA/FC-PGA2 packages processor is not a simple single value. Instead, many factors are needed to determine the over/undershoot specification.
Intel® Celeron® Processor up to 1.10 GHz 3.4.6 Determining if a System meets the Overshoot/Undershoot Specifications (FC-PGA/FC-PGA2 Packages) The overshoot/undershoot specifications listed in the following tables specify the allowable overshoot/undershoot for a single overshoot/undershoot event. However most systems will have multiple overshoot and/or undershoot events that each have their own set of parameters (duration, AF and magnitude).
Intel® Celeron® Processor up to 1.10 GHz Table 39. 33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance at Processor Pins (FC-PGA/FC-PGA2 Packages) Overshoot/ Undershoot Magnitude Maximum Pulse Duration at Tj = 80 °C (ns) Maximum Pulse Duration at Tj = 90 °C (ns) AF = 0.01 AF = 0.01 AF = 0.1 AF = 1 AF = 0.1 AF = 1 2.18 V 60 7.6 0.76 36 3.6 0.36 2.13 V 60 14.8 1.48 60 6.4 0.64 2.08 V 60 27.2 2.7 60 12.8 1.2 2.03 V 60 50 5 60 24 2.2 1.98 V 60 60 9.1 60 44 4 1.
Intel® Celeron® Processor up to 1.10 GHz 3.5 Non-AGTL+ Signal Quality Specifications and Measurement Guidelines There are three signal quality parameters defined for non-AGTL+ signals: overshoot/undershoot, ringback, and settling limit. All three signal quality parameters are shown in Figure 16 for the nonAGTL+ signal group. Figure 16.
Intel® Celeron® Processor up to 1.10 GHz 4.0 Thermal Specifications and Design Considerations This section provides needed data for designing a thermal solution. However, for the correct thermal measuring processes, refer to AP-905, Intel® Pentium® III Processor Thermal Design Guidelines (Order Number 245087). For the FC-PGA/FC-PGA2 using flip chip pin grid array packaging technology, Intel specifies the junction temperature (Tjunction). For the S.E.P.
Intel® Celeron® Processor up to 1.10 GHz Table 40. Processor Power for the PPGA and FC-PGA Packages Processor Core Frequency L2 Cache Size (KB) Processor Thermal Design Power2,3 (W) up to CPUID 0686h Processor Thermal Design Power2,3 (W) for CPUID 068Ah Power Density 5 (W/cm2) For CPUID 0686h Power Density 5 (W/cm2) For CPUID 068Ah Min TCASE (°C) Max TCASE (°C) Max10 TJUNCTION (°C) TJUNCTION Offset 6 (°C) 333 MHz 128 19.7 NA NA NA 5 85 NA NA 366 MHz 128 21.
Intel® Celeron® Processor up to 1.10 GHz Table 41. Intel® Celeron® Processor for the FC-PGA2 Package Thermal Design Power 1 Processor Processor Core Frequency (MHz) System Bus Frequency (MHz) Processor Thermal Design Power 2,3 CPUID 068Ah (W) Maximum Tcase4 (°C) 900 900 100 30.0 72 5 950 950 100 32.0 72 5 1 GHz 1000 100 33.9 69 5 Additional Notes NOTES: 1. These values are specified at nominal VCCCORE for the processor pins. 2.
Intel® Celeron® Processor up to 1.10 GHz 4.1.1 Thermal Diode The Celeron processor incorporates an on-die diode that can be used to monitor the die temperature. A thermal sensor located on the motherboard or a standalone measurement kit may monitor the die temperature of the Intel Celeron processor for thermal management purposes. Table 42 to Table 44 provide the diode parameter and interface specifications.
Intel® Celeron® Processor up to 1.10 GHz 5.0 Mechanical Specifications There are three package technologies which Celeron processors use. They are the S.E.P. Package, the PPGA package, and the FC-PGA/FC-PGA2 packages. The S.E.P. Package and FC-PGA/ FC-PGA2 packages contain the processor core and passive components, while the PPGA package does not have passive components. The processor edge connector defined in this document is referred to as the “SC242 connector.
Intel® Celeron® Processor up to 1.10 GHz Figure 19. Processor Substrate Dimensions (S.E.P. Package) +.007 .062 -.005 -Z- -Y- 2.608 27.4 mm SR Opening Square 25.4 mm Copper Slug Square 1.660 1.370 -Y.615 .323 .814 1.196 3.804 -Y- Figure 20. Processor Substrate Primary/Secondary Side Dimensions (S.E.P. Package) .025 Typ Max. Non-Keepout Area .025 Typ Max. Non-Keepout Area Secondary Side There Will be No Components on Secodonary Side -D- -G-E- -H- .025 Typ Max. Non-Keepout Area .025 Typ Max.
Intel® Celeron® Processor up to 1.10 GHz Table 45. S.E.P. Package Signal Listing by Pin Number Pin No. A1 Datasheet Pin Name VTT Signal Buffer Type Table 45. S.E.P. Package Signal Listing by Pin Number Pin No.
Intel® Celeron® Processor up to 1.10 GHz Table 45. S.E.P. Package Signal Listing by Pin Number Pin No. 72 Pin Name Signal Buffer Type Table 45. S.E.P. Package Signal Listing by Pin Number Pin No.
Intel® Celeron® Processor up to 1.10 GHz Table 45. S.E.P. Package Signal Listing by Pin Number Pin No. B25 Datasheet Pin Name Signal Buffer Type Table 45. S.E.P. Package Signal Listing by Pin Number Pin No.
Intel® Celeron® Processor up to 1.10 GHz Table 45. S.E.P. Package Signal Listing by Pin Number Pin No.
Intel® Celeron® Processor up to 1.10 GHz Table 46. S.E.P. Package Signal Listing by Signal Name Pin Name A3# Datasheet Pin No. B98 Signal Buffer Type Table 46. S.E.P. Package Signal Listing by Signal Name Pin Name Pin No.
Intel® Celeron® Processor up to 1.10 GHz Table 46. S.E.P. Package Signal Listing by Signal Name Pin Name 76 Pin No. Signal Buffer Type Table 46. S.E.P. Package Signal Listing by Signal Name Pin Name Pin No.
Intel® Celeron® Processor up to 1.10 GHz Table 46. S.E.P. Package Signal Listing by Signal Name Pin Name Reserved Datasheet Pin No. A117 Signal Buffer Type Reserved for Pentium II processor Table 46. S.E.P. Package Signal Listing by Signal Name Pin Name Pin No.
Intel® Celeron® Processor up to 1.10 GHz Table 46. S.E.P. Package Signal Listing by Signal Name Pin Name 78 Pin No. Signal Buffer Type Table 46. S.E.P. Package Signal Listing by Signal Name Pin Name Pin No.
Intel® Celeron® Processor up to 1.10 GHz 5.2 PPGA Package This section defines the mechanical specifications and signal definitions for the Celeron processor in the PPGA packages. 5.2.1 PPGA Package Materials Information Figure 21 and Table 47 are provided to aid in the design of a heatsink and clip. Figure 21. Package Dimensions (PPGA Package) Top View Bottom View Heat Slug D Solder Resist D1 S1 D B1 45° x 0.
Intel® Celeron® Processor up to 1.10 GHz Table 47. Package Dimensions (PPGA Package) Millimeters Symbol Min Max A 1.83 2.23 A1 A2 Inches Notes Min Max 0.072 0.088 1.00 2.72 Notes 0.039 3.33 0.107 0.131 B 0.40 0.51 0.016 0.020 D 49.43 49.63 1.946 1.954 D1 45.59 45.85 1.795 1.805 D2 25.15 25.65 0.099 1.010 e1 2.29 2.79 0.090 0.110 L 3.05 3.30 0.120 0.130 N S1 370 1.52 Lead Count 2.54 370 0.060 Lead Count 0.100 Table 48.
Intel® Celeron® Processor up to 1.10 GHz 5.2.2 PPGA Package Signal Listing Figure 22.
Intel® Celeron® Processor up to 1.10 GHz Table 49. PPGA Package Signal Listing by Pin Number Pin No. 82 Pin Name Signal Buffer Type Table 49. PPGA Package Signal Listing by Pin Number Pin No. Pin Name Signal Buffer Type A3 D29# AGTL+ I/O AD4 A31# AGTL+ I/O A5 D28# AGTL+ I/O AD6 VREF5 Power/Other A7 D43# AGTL+ I/O AD32 VCCCORE Power/Other VSS Power/Other A9 D37# AGTL+ I/O AD34 A11 D44# AGTL+ I/O AD36 VCC1.
Intel® Celeron® Processor up to 1.10 GHz Table 49. PPGA Package Signal Listing by Pin Number Pin No. Datasheet Pin Name Signal Buffer Type Table 49. PPGA Package Signal Listing by Pin Number Pin No.
Intel® Celeron® Processor up to 1.10 GHz Table 49. PPGA Package Signal Listing by Pin Number Pin No. 84 Pin Name Signal Buffer Type Table 49. PPGA Package Signal Listing by Pin Number Pin No.
Intel® Celeron® Processor up to 1.10 GHz Table 49. PPGA Package Signal Listing by Pin Number Pin No. Datasheet Pin Name Signal Buffer Type Table 49. PPGA Package Signal Listing by Pin Number Pin No.
Intel® Celeron® Processor up to 1.10 GHz Table 49. PPGA Package Signal Listing by Pin Number Pin No. 86 Pin Name Signal Buffer Type Table 49. PPGA Package Signal Listing by Pin Number Pin No.
Intel® Celeron® Processor up to 1.10 GHz Table 50. PPGA Package Signal Listing in Order by Signal Name Pin Name Datasheet Pin No. Signal Buffer Type Table 50. PPGA Package Signal Listing in Order by Signal Name Pin Name Pin No.
Intel® Celeron® Processor up to 1.10 GHz Table 50. PPGA Package Signal Listing in Order by Signal Name Pin Name 88 Pin No. Signal Buffer Type Table 50. PPGA Package Signal Listing in Order by Signal Name Pin Name D39# D10 AGTL+ I/O PICD0 D40# C15 AGTL+ I/O D41# D14 AGTL+ I/O D42# D12 D43# A7 D44# D45# D46# D47# Pin No.
Intel® Celeron® Processor up to 1.10 GHz Table 50. PPGA Package Signal Listing in Order by Signal Name Pin Name Datasheet Pin No. Signal Buffer Type Table 50. PPGA Package Signal Listing in Order by Signal Name Pin Name Pin No. Signal Buffer Type Reserved Q33 Reserved for Future Use VCC2.
Intel® Celeron® Processor up to 1.10 GHz Table 50. PPGA Package Signal Listing in Order by Signal Name Pin Name 90 Pin No. Signal Buffer Type Table 50. PPGA Package Signal Listing in Order by Signal Name Pin Name Pin No.
Intel® Celeron® Processor up to 1.10 GHz Table 50. PPGA Package Signal Listing in Order by Signal Name Pin Name Datasheet Pin No. VSS P32 VSS VSS VSS VSS Signal Buffer Type Table 50. PPGA Package Signal Listing in Order by Signal Name Pin Name Pin No.
Intel® Celeron® Processor up to 1.10 GHz 5.3 FC-PGA/FC-PGA2 Packages This section defines the mechanical specifications and signal definitions for the Intel Celeron processor in the FC-PGA and FC-PGA2 packages. 5.3.1 FC-PGA Mechanical Specifications Figure 23 is provided to aid in the design of heatsink and clip solutions as well as demonstrate where pin-side capacitors will be located on the processor. Table 51 provides the measurements for these dimensions in both inches and millimeters. Figure 23.
Intel® Celeron® Processor up to 1.10 GHz Table 51. Package Dimensions (FC-PGA Package) Millimeters Symbol Min Max A1 0.787 A2 Inches Notes Min Max 0.889 0.031 0.035 1.000 1.200 0.039 0.047 B1 11.183 11.285 0.440 0.445 B2 9.225 9.327 0.363 0.368 C1 23.495 max 0.925 max C2 21.590 max 0.850 max D 49.428 49.632 1.946 1.954 D1 45.466 45.947 1.790 1.810 G1 0.000 17.780 1 0.000 0.700 G2 0.000 17.780 1 0.000 0.700 G3 0.000 0.889 1 0.000 0.035 H 2.
Intel® Celeron® Processor up to 1.10 GHz 5.3.2 Mechanical Specifications (FC-PGA2 Package) Figure 24 is provided to aid in the design of heatsink and clip solutions as well as demonstrate where pin-side capacitors will be located on the processor. Table 53 lists the measurements for these dimensions in both inches and millimeters. Figure 24.
Intel® Celeron® Processor up to 1.10 GHz Table 53. Package Dimensions (FC-PGA2 Package) Millimeters Inches Symbol Minimum Maximum A1 2.266 A2 Notes Minimum Maximum 2.690 0.089 0.106 0.980 1.180 0.038 0.047 B1 30.800 31.200 1.212 1.229 B2 30.800 31.200 1.212 1.229 C1 33.000 max 1.299 max C2 33.000 max 1.299 max D 49.428 49.632 1.946 1.954 D1 45.466 45.974 1.790 1.810 G1 0.000 17.780 0.000 0.700 G2 0.000 17.780 0.000 0.700 G3 0.000 0.889 0.000 0.
Intel® Celeron® Processor up to 1.10 GHz 5.3.2.1 Recommended Mechanical Keep-Out Zones (FC-PGA2 Package) Figure 25. Volumetric Keep-Out Figure 26.
Intel® Celeron® Processor up to 1.10 GHz 5.3.3 FC-PGA/FC-PGA2 Package Signal List Figure 27.
Intel® Celeron® Processor up to 1.10 GHz Table 55. FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name Pin Name 98 Pin Signal Group Table 55.
Intel® Celeron® Processor up to 1.10 GHz Table 55. FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name Pin Name Datasheet Pin Signal Group Table 55.
Intel® Celeron® Processor up to 1.10 GHz Table 55. FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name Pin Name 100 Pin Signal Group Table 55.
Intel® Celeron® Processor up to 1.10 GHz Table 55.
Intel® Celeron® Processor up to 1.10 GHz Table 55. FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name Pin Name 102 Pin Signal Group Table 55.
Intel® Celeron® Processor up to 1.10 GHz Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number Pin No. Datasheet Pin Name Signal Group Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number Pin No. Pin Name Signal Group A3 D29# AGTL+ I/O AD32 VCCCORE Power/Other A5 D28# AGTL+ I/O AD34 GND Power/Other A7 D43# AGTL+ I/O AD36 VCC1.
Intel® Celeron® Processor up to 1.10 GHz Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number Pin No. AJ1 104 Pin Name A21# Signal Group Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number Pin No.
Intel® Celeron® Processor up to 1.10 GHz Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number Pin No. Datasheet Pin Name Signal Group Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number Pin No.
Intel® Celeron® Processor up to 1.10 GHz Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number Pin No. 106 Pin Name Signal Group Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number Pin No.
Intel® Celeron® Processor up to 1.10 GHz Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number Pin No. Q5 Datasheet Pin Name GND Signal Group Power/Other Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number Pin No.
Intel® Celeron® Processor up to 1.10 GHz 5.4 Processor Markings (PPGA/FC-PGA/FC-PGA2 Packages) Figure 28 through Figure 30 show processor top-side markings; the markings aid in the identification of a Celeron processor for the PGA370 socket. Package dimension measurements are provided in Table 47 for the PPGA package, Table 51 for the FC-PGA package, and Table 53 for the FC-PGA2 package. Figure 28.
Intel® Celeron® Processor up to 1.10 GHz 5.5 Heatsink Volumetric Keepout Zone Guidelines When designing a system platform it is necessary to ensure sufficient space is left for a heatsink to be installed without mechanical interference. Due to the large number of proprietary heatsink designs, Intel cannot specify a keepout zone that covers all passive and active-fan heatsinks.
Intel® Celeron® Processor up to 1.10 GHz 6.0 Boxed Processor Specifications The Celeron processor is also offered as an Intel boxed processor in the FC-PGA/FC-PGA2, PPGA, and S.E.P. Packages. Intel boxed processors are intended for system integrators who build systems from motherboards and standard components. The boxed Celeron processor in the S.E.P. Package is supplied with an attached fan heatsink.
Intel® Celeron® Processor up to 1.10 GHz Figure 31. Retention Mechanism for the Boxed Intel® Celeron® Processor in the S.E.P. Package Figure 32. Side View Space Requirements for the Boxed Processor in the S.E.P. Package 1.386 (A) S.E.P.P. Fan Heatsink 242-Contact Slot Connector 0.
Intel® Celeron® Processor up to 1.10 GHz Figure 33. Front View Space Requirements for the Boxed Processor in the S.E.P. Package 5.40 (E) 4.74 (D) 2.02 (C) Table 57. Boxed Processor Fan Heatsink Spatial Dimensions for the S.E.P. Package Fig. Ref. Label 6.1.1.1 Dimensions (Inches) Min Typ Max A Fan Heatsink Depth (see Figure 27) B Fan Heatsink Height from Motherboard (see Figure 27) 1.40 C Fan Heatsink Height (see Figure 31) 2.00 D Fan Heatsink Width (see Figure 31) 4.
Intel® Celeron® Processor up to 1.10 GHz 6.1.2 Mechanical Specifications for the PPGA Package This section documents the mechanical specifications for the fan heatsink of the boxed Celeron processor in the PPGA package. The boxed processor in the PPGA package ships with an unattached fan heatsink which has an integrated clip. Figure 34 shows a mechanical representation of the boxed Intel Celeron processor in the PPGA package.
Intel® Celeron® Processor up to 1.10 GHz 6.1.2.1 Boxed Processor Heatsink Weight The heatsink for the boxed Intel Celeron processor in the PPGA package will not weigh more than 180 grams. 6.1.3 Mechanical Specifications for the FC-PGA/FC-PGA2 Packages This section documents the mechanical specifications of the fan heatsink for the boxed Intel Celeron processor in the FC-PGA/FC-PGA2 (Flip-Chip Pin Grid Array) packages.
Intel® Celeron® Processor up to 1.10 GHz 6.1.3.1 Boxed Processor Heatsink Weight The heatsink for the boxed Intel Celeron processor in the FC-PGA/FC-PGA2 packages will not weigh more than 180 grams. 6.2 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution utilized by the boxed processors. 6.2.1 Thermal Requirements for the Boxed Intel® Celeron® Processor 6.2.1.
Intel® Celeron® Processor up to 1.10 GHz Figure 39. Side View Airspace Requirements for the Boxed Intel® Celeron® Processor in the FC-PGA/FC-PGA2 and PPGA Packages Measure ambient temperature 0.3" above center of fan inlet 0.20 Min Air Space 0.20 Min Air Space Fan Heatsink Processor Figure 40.
Intel® Celeron® Processor up to 1.10 GHz 6.2.1.2 Boxed Processor Thermal Cooling Solution Clip The boxed processor thermal solution requires installation by a system integrator to secure the thermal cooling solution to the processor after it is installed in the 370-pin socket ZIF socket. Motherboards designed for use by system integrators should take care to consider the implications of clip installation and potential scraping of the motherboard PCB underneath the 370-pin socket attach tabs.
Intel® Celeron® Processor up to 1.10 GHz The boxed Intel Celeron processors in the PPGA package at 500 MHz and below are shipped with an unattached fan heatsink with two wire power-supply cables. These two wire fans do NOT support the motherboard-mounted fan speed monitor feature. The Intel Celeron processor at 533 MHz and above ship with unattached fan heatsinks that have three power-supply cables. These three wire fans DO support the motherboard-mounted fan speed monitor feature.
Intel® Celeron® Processor up to 1.10 GHz Figure 43. Motherboard Power Header Placement for the S.E.P. Package 242-Contact Slot Connector Fan power connector location (1.56 inches above motherboard 1.428" 1.449" r = 4.75" Motherboard fan power header should be positioned within 4.75 inches of the fan power connector (lateral distance). Figure 44. Motherboard Power Header Placement Relative to the 370-pin Socket R = 4.00" PGA370 ppga1.
Intel® Celeron® Processor up to 1.10 GHz 7.0 Processor Signal Description Table 59 provides an alphabetical listing of all Celeron processor signals. The tables at the end of this section summarize the signals by direction (output, input, and I/O). Note: Unless otherwise noted, the signals apply to S.E.P., PPGA, and FC-PGA/FC-PGA2 Packages. Table 59.
Intel® Celeron® Processor up to 1.10 GHz Table 59. Alphabetical Signal Reference (Sheet 2 of 7) Signal BPRI# BSEL[1:0] BR0# Type Description I The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the Intel Celeron processor system bus. It must connect the appropriate pins of all Intel Celeron processor system bus agents.
Intel® Celeron® Processor up to 1.10 GHz Table 59. Alphabetical Signal Reference (Sheet 3 of 7) Signal Description I The EDGCTRL input provides AGTL+ edge control and should be pulled up to VCCCORE with a 51 Ω ± 5% resistor. NOTE: This signal is NOT used on the FC-PGA/FC-PGA2 packages. EMI (S.E.P.P. only) I EMI pins should be connected to motherboard ground and/or to chassis ground through zero ohm (0 Ω) resistors.
Intel® Celeron® Processor up to 1.10 GHz Table 59. Alphabetical Signal Reference (Sheet 4 of 7) Signal Type Description I The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of all APIC Bus agents, including all processors and the core logic or I/O APIC component. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt.
Intel® Celeron® Processor up to 1.10 GHz Table 59. Alphabetical Signal Reference (Sheet 5 of 7) Signal Type Description I/O The REQ[4:0]# (Request Command) signals must connect the appropriate pins of all processor system bus agents. They are asserted by the current bus owner over two clock cycles to define the currently active transaction type. RESET# I Asserting the RESET# signal resets the processor to a known state and invalidates the L1 cache without writing back any of the contents.
Intel® Celeron® Processor up to 1.10 GHz Table 59. Alphabetical Signal Reference (Sheet 6 of 7) Signal Description I The SMI# (System Management Interrupt) signal is asserted asynchronously by system logic. On accepting a System Management Interrupt, processors save the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.
Intel® Celeron® Processor up to 1.10 GHz Table 59. Alphabetical Signal Reference (Sheet 7 of 7) Signal Type Description VCOREDET (PGA packages only) O The VCOREDET signal will float for 2.0 V core processors and will be grounded for the Celeron® FC-PGA/FC-PGA2 processor with a 1.5V core voltage. O The VID (Voltage ID) pins can be used to support automatic selection of power supply voltages. These pins are not signals, but are either an open circuit or a short circuit to VSS on the processor.
Intel® Celeron® Processor up to 1.10 GHz Table 61.
Intel® Celeron® Processor up to 1.10 GHz Table 62.