Datasheet

Board Status and Error Messages

Table 42. Port 80h POST Codes (continued)

Port 80 Code Progress Code Enumeration

CPU DXE Phase

0x47 CPU DXE Phase begin

0x48 Refresh memory space attributes according to MTRRs

0x49 Load the microcode if needed

0x4A Initialize strings to HII database

0x4B Initialize MP support

0x4C CPU DXE Phase End

CPU DXE SMM Phase

0x4D CPU DXE SMM Phase begin

0x4E Relocate SM bases for all APs

0x4F CPU DXE SMM Phase end

I/O BUSES

0x50 Enumerating PCI buses

0x51 Allocating resources to PCI bus

0x52 Hot Plug PCI controller initialization

USB

0x58 Resetting USB bus

0x59 Reserved for USB

ATA/ATAPI/SATA

0x5A Resetting PATA/SATA bus and all devices

0x5B Reserved for ATA

BDS

0x60 BDS driver entry point initialize

0x61 BDS service routine entry point (can be called multiple times)

0x62 BDS Step2

0x63 BDS Step3

0x64 BDS Step4

0x65 BDS Step5

0x66 BDS Step6

0x67 BDS Step7

0x68 BDS Step8

0x69 BDS Step9

0x6A BDS Step10

0x6B BDS Step11

0x6C BDS Step12

0x6D BDS Step13

0x6E BDS Step14

0x6F BDS return to DXE core (should not get here)

continued