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Pentium® III Xeon™ Processor at 500 and

550 MHz

Datasheet

Product Features

The Intel

Pentium

III Xeon™ processor is designed for mid-range to high-end servers and workstations, and is binary

compatible with previous Intel Architecture processors. The Pentium III Xeon processor provides the best performance

available for applications running on advanced operating systems such as Windows* 95, Windows NT, and UNIX*. The

Pentium III Xeon processor is scalable to four processors in a multiprocessor system and extends the power of the

Pentium

Pro processor with new features designed to make this processor the right choice for powerful workstation,

advanced server management, and mission-critical applications. Pentium III Xeon processor-based workstations offer

the memory architecture required by the most demanding workstation applications and workloads. Specific features of

the Pentium III Xeon processor address platform manageability to meet the needs of a robust IT environment, maximize

system up time and ensure optimal configuration and operation of servers. The Pentium III Xeon processor enhances the

ability of server platforms to monitor, protect, and service the processor and its environment.

n Binary compatible with applications

running on previous members of the Intel

microprocessor family

n Optimized for 32-bit applications running

on advanced 32-bit operating systems

n Dynamic Execution micro architecture

n Dual Independent Bus architecture:

Separate dedicated external 100MHz

System Bus and dedicated internal cache

bus operating at full processor core speed

n Power Management capabilities

— System Management mode

— Multiple low-power states

n SMBus interface to advanced

manageability features

n Intel

processor serial number

n Single Edge Contact (S.E.C.) cartridge

packaging technology; the S.E.C. cartridge

delivers high performance processing and

bus technology in mid-range to high-end

servers and workstations

n 100 MHz system bus speeds data transfer

between the processor and the system

n Integrated high performance16K

instruction and 16K data, nonblocking,

level-one cache

n Available in 512K, 1 M, or 2 M unified,

nonblocking level-two cache

n Enables systems which are scaleable up to

four processors and 64 GB of physical

memory

n Streaming SIMD Extensions for enhanced

video, sound and 3D performance

Order Number: 245094-002

February 2000

Summary of content (112 pages)

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Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet Product Features n n n n n n n Binary compatible with applications running on previous members of the Intel microprocessor family Optimized for 32-bit applications running on advanced 32-bit operating systems Dynamic Execution micro architecture Dual Independent Bus architecture: Separate dedicated external 100MHz System Bus and dedicated internal cache bus operating at full processor core speed Power Management capabilities — System Managemen
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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Contents 1.0 Introduction.........................................................................................................................9 1.1 1.2 2.0 Electrical Specifications....................................................................................................11 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 3.0 3.3 System Bus Clock Signal Quality Specifications.................................................
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Pentium® III Xeon™ Processor at 500 and 550 MHz 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 5.0 Thermal Specifications and Design Considerations.........................................................49 5.1 5.2 6.0 7.3 Introduction .........................................................................................................71 Mechanical Specifications...................................................................................71 7.2.1 Boxed Processor Heatsink Dimensions .........................
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Pentium® III Xeon™ Processor at 500 and 550 MHz 8.2 9.0 Appendix ..........................................................................................................................86 9.1 Datasheet Integration Tool (Logic Analyzer) Considerations ...............................................86 Alphabetical Signals Reference ..........................................................................86 9.1.1 A[35:03]# (I/O)............................................................................
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Pentium® III Xeon™ Processor at 500 and 550 MHz 9.2 9.1.47 SLP# (I) ..................................................................................................96 9.1.48 SMBALERT# (O)....................................................................................96 9.1.49 SMBCLK (I) ............................................................................................96 9.1.50 SMBDAT (I/O) ........................................................................................96 9.1.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Top View of Cartridge Insertion Pressure Points ................................................61 Front View of Connector Mating Details..............................................................61 Boxed Pentium® III Xeon™ Processor................................................................71 Side View Space Requirements for the Boxed Processor ..................................
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Pentium® III Xeon™ Processor at 500 and 550 MHz 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 8 Byte Write SMBus Packet ...................................................................................43 Write Byte SMBus Packet ...................................................................................45 Read Byte SMBus Packet...................................................................................45 Send Byte SMBus Packet ..............................
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Pentium® III Xeon™ Processor at 500 and 550 MHz 1.0 Introduction The Pentium III Xeon processor is a follow-on to the Pentium Pro and Pentium® II Xeon processors. The Pentium III Xeon processor, like the Pentium Pro and Pentium II Xeon processors, implements a Dynamic Execution micro-architecture — a unique combination of multiple branch prediction, data flow analysis, and speculative execution.
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Pentium® III Xeon™ Processor at 500 and 550 MHz The term “Pentium III Xeon processor” refers to the cartridge package which interfaces to a host system board through a SC330 Connector. Pentium III Xeon processors include a processor core, a level 2 cache, system bus termination and various system management features. The Pentium III Xeon processor includes a thermal plate for cooling solution attachment and a protective cover. 1.1.1 S.E.C.
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Pentium® III Xeon™ Processor at 500 and 550 MHz • Pentium® II Xeon™ Processor Support Component Vendor List (http://developer.intel.
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Pentium® III Xeon™ Processor at 500 and 550 MHz provide termination for each Pentium III Xeon processor. These specifications assume the equivalent of 6 AGTL+ loads and termination resistors to ensure the proper timings on rising and falling edges. See test conditions described with each specification. Due to the existence of termination on each of up to 4 processors in a Pentium III Xeon processor system, the AGTL+ bus is typically not a daisy chain topology as in previous P6 family processor systems.
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Pentium® III Xeon™ Processor at 500 and 550 MHz when the part is powering on, or entering/exiting low power states, is provided on the voltage regulation module (VRM) defined in the VRM 8.2 DC–DC Converter Design Guidelines and the VRM 8.3 DC–DC Converter Design Guidelines. The input to VCCCORE should be capable of delivering a recommended minimum dICCCORE/dt defined in Table 6 while maintaining the required tolerances defined in Table 5. See the Pentium® III Xeon™ Processor Power Distribution Guidelines.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 1.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Figure 1. Timing Diagram of Clock Ratio Signals BCLK RESET# CRESET# ≤ Final Ratio Ratio Pins# Compatibility Final Ratio Figure 2. Logical Schematic for Clock Ratio Pin Sharing 2.5 V 2.5 V 1K Ω Mux A20M# 1-4 Processors IGNNE# LINT1/NMI LINT0/INTR Set Ratio: CRESET# Note: 2.4.1 Signal Integrity issues may require this circuit to be modified.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 2.5 Voltage Identification The Pentium III Xeon processor contains five voltage identification pins for core voltage selection and five voltage identification pins for L2 cache voltage selection. These pins may be used to support automatic selection of both power supply voltages. VID_CORE[4:0] controls the voltage supply to the processor core and VID_L2[4:0] controls the voltage supply to the L2 cache. Both use the same encoding as shown in Table 2.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 2. Core and L2 Voltage Identification Definition 1, 2 (Sheet 2 of 2) Processor Pins VID4 VID3 VID2 VID1 VID0 VCC 1 0 0 0 1 3.4 1 0 0 0 0 3.5 1 1 1 1 1 no core Core3 L23 NOTES 1. 0 = Processor pin connected to VSS, 1 = Open on processor; may be pulled up to TTL VIH on baseboard. See the VRM 8.2 DC–DC Converter Design Guidelines and/or the VRM 8.3 DC–DC Converter Design Guidelines. 2.
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Pentium® III Xeon™ Processor at 500 and 550 MHz When tying any signal to power or ground, a resistor will also allow for system testability. For correct operation when using a logic analyzer interface, refer to Section 8.0 for design considerations. 2.7 System Bus Signal Groups In order to simplify the following discussion, the system bus signals have been combined into groups by buffer type.
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Pentium® III Xeon™ Processor at 500 and 550 MHz NOTES 1. The BR0# pin is the only BREQ# signal that is bi-directional. The internal BREQ# signals are mapped onto BR# pins based on a processor’s agent ID. See Section 9.0 for more information. 2. For information on these signals, see Section 9.0. 3. These signals are specified fo r 2.5V operation. 4. VCCCORE is the power supply for the Pentium® III Xeon™ processor core. VCCL2 is the power supply for the L2 cache memory.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 2.9 Maximum Rating Table 4 contains Pentium III Xeon processor stress ratings. Functional operation at the absolute maximum and minimum is not implied nor guaranteed. The processor should not receive a clock while subjected to these conditions. Functional operating conditions are given in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Most of the signals on the Pentium III Xeon processor system bus are in the AGTL+ signal group. These signals are specified to be terminated to VTT. The DC specifications for these signals are listed in Table 7. To ease connection with other devices, the Clock, CMOS, APIC, SMBus and TAP signals are designed to interface at non-AGTL+ levels. The DC specifications for these pins are listed in Table 8 and Table 9.
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Pentium® III Xeon™ Processor at 500 and 550 MHz connector is specified to have a pin self-inductance of 6.0 nH maximum, a pin-to-pin capacitance of 2 pF (maximum at 1 MHz), and an average contact resistance over the 6 V TT pins of 15 mΩ maximum. 7. These are the tolerance requirements, ac ross a 20MHz bandwidth, at the processor edge fingers. The requirements at the processor edge fingers account for voltage drops (and impedance discontinuities) at the processor edge fingers and to the processor core.
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Pentium® III Xeon™ Processor at 500 and 550 MHz negative current flow due to the active pull-up to VCCCORE in the Pentium III Xeon processor will not be seen at the processor fingers. 9. The current specified is also for AutoHALT state. 10.Maximum values are specified by design/characterization at nominal V CC and at the SC330 connector pins. 11.Based on simulation and averaged over the duration of any change in current.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 8. CMOS, TAP, Clock and APIC Signal Groups, DC Specifications at the Processor Core Symbol Parameter Min Max Unit V Notes VIL Input Low Voltage -0.3 0.7 VIH Input High Voltage 1.7 2.625 V 2.5 V + 5% maximum VOL Output Low Voltag 0.5 V Measured at 24mA VOH Output High Voltage 2.625 V All outputs are open-drai n to 2.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 10. Pentium® III Xeon™ Processor Internal Parameters for the AGTL+ Bus Symbol Parameter RTT Termination Resistor VREF Bus Reference Voltage Min Typ Max Units Notes 150 W 1 2/3 VTT V 2 NOTES 1. The Pentium ® III Xeon™ processor contains 1% AGTL+ termination resistors at the end of the signal trace on the processor substrate. 2. VREF is generated on the processor substrate. 2.
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Pentium® III Xeon™ Processor at 500 and 550 MHz allowed between adjacent cycles. Positive or negative jitter of up to 250 ps is tolerated, but will result in up to 100 ps of AGTL+ I/O and CMOS timing degradation (i.e., timing parameters T7-9 and T11-13 will all increase by 100 ps). Thus a system with jitter of 250 ps would need flight times that are 300 ps (100 ps additional jitter + 100 ps I/O timing degradation for both the source and receiver) better than a system with jitter of 150 ps. 7.
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Pentium® III Xeon™ Processor at 500 and 550 MHz BCLK has met the BCLK AC specifications in Table 11 for at least 10 clock cycles. PWRGOOD must rise glitch-free and monotonica l y to 2.5V. 8. If the BCLK signal meets its AC specification withi n 150ns of turning on then the PWRGOOD Inactive Pulse Width specification is waived and BCLK may start after PWRGOOD is asserted. PWRGOOD must still remain below VIL_MAX until all the voltage planes meet the voltage tolerance specifications. Table 14.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 16. System Bus AC Specifications (TAP Connection) at the Processor Core Min Max Unit 16.667 MHz 1 T# Parameter Figure Notes T30: TCK Frequency T31: TCK Period 60.0 ns 4 T32: TCK High Time 25.0 ns 4 @1.7 V 2 T33: TCK Low Time 25.0 ns 4 @0.7 V 2 T34: TCK Rise Time 3.0 5.0 ns 4 (0.7 V–1. 7V) 2, 3 T35: TCK Fall Time 3.0 5.0 ns 4 (1.7 V–0. 7V) 2, 3 T36: TRST# Pulse Width 40.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Figure 4 through Figure 12 are to be used in conjunction with the DC specification and AC timings tables. Figure 4. BCLK, PICCLK, TCK Generic Clock Waveform Tr Th 2.0 V 1.25 V Clock 0.5 V Tf Tl Tp Tr = T5, T25, T34 (Rise Time) Tf = T6, T26, T36 (Fall Time) Th = T3, T23, T32 (High Time) Tl = T4, T24, T33 (Low Time) Tp = T1, T22, T31 (BCLK, PICCLK, TCK, Period) Figure 5. SMBCLK Clock Waveform Th Tr 2.97V 2.46V 0.84V SCLK 0.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Figure 7. Setup and Hold Timings Clock Vclk Ts Signal Th V Valid Ts = T8, T12, T27 (Setup Time) Th = T9, T13, T28 (Hold Time) V = 2/3 VTT for the AGTL+ signal group; 1.25V for the CMOS, and APIC signal groups Vclk = 1.25V for BCLK, and PICCLK Figure 8. FRC Mode BCLK to PICCLK Timing BCLK 1.25 V Lag PICCLK 1.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Figure 9.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Figure 11. Test Timings (Boundary Scan) 1.25V TCK Tv Tw Tr Ts 1.25V TDI, TMS Non-Test Input Signals Tx Tu Ty Tz TDO Non-Test Output Signals Tr = T43 (All Non-Test Inputs Setup Time) Ts = T44 (All Non-Test Inputs Hold Time) Tu = T40 (TDO Float Delay) Tv = T37 (TDI, TMS Setup Time) Tw = T38 (TDI, TMS Hold Time) Tx = T39 (TDO Valid Delay) Ty = T41 (All Non-Test Outputs Valid Delay) Tz = T42 (All Non-Test Outputs Float Delay) Figure 12.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 3.1 System Bus Clock Signal Quality Specifications Table 18 describes the signal quality specifications at the processor core pad for the Pentium III Xeon processor system bus clock (BCLK) signal. Figure 13 shows the signal quality waveform for the system bus clock at the processor core pads. Please see Table 11 for the definition of T numbers and Table 18 for the definition of V numbers. Table 18.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 3.2.1 AGTL+ Ringback Tolerance Specifications Table 19 provides the AGTL+ signal quality specifications for Pentium III Xeon processors for use in simulating signal quality at the processor core pads. Figure 14 describes the signal quality waveform for AGTL+ signals at the processor core pads. For more information on the AGTL+ interface, see the Pentiu ® II Processor Developer’s Manual. Table 19.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 20. AGTL+ Overshoot/Undershoot Guidelines at the Processor Core 3.3 Guideline Transition Signal Must Maintain Unit Figure Overshoot Undershoot 0→1 < 2.7 V 15 1→0 > -0.7 V 15 Non-AGTL+ Signal Quality Specifications There are three signal quality parameters defined for non-AGTL+ signals: overshoot/undershoot, ringback, and settling limit.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 22. Signal Ringback Specifications fo r 2.5V Tolerant Signal Simulation at the Processor Core 3.3.3 Input Signal Group Transition Maximum Ringback (with Input Diodes Present) Unit Figure Non-AGTL+ Signals 0→1 1.7 V 15 Non-AGTL+ Signals 1→0 0.7 V 15 2.5 V Tolerant Buffer Settling Limit Guideline Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach before its next transition.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 4.2 Low Power States and Clock Control The Pentium III Xeon processor allows the use of Auto HALT, Stop-Grant, and Sleep states to reduce power consumption by stopping the clock to specific internal sections of the processor, depending on each particular state. There is no Deep Sleep state on the Pentium III Xeon processor. Refer to for the following sections on low power states for the Pentium III Xeon processor.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Figure 16. Stop Clock State Machine HALT Instruction and HALT Bus Cycle Generated 2. Auto HALT Power Down State BCLK running. Snoops and interrupts allowed. INIT#, BINIT#, INTR, NMI, SMI#, RESET# STPC LK# Snoop Event Occurs Snoop Event Serviced STPC LK# 4. HALT/Grant Snoop State BCLK running. Service snoops to caches. De-a ssert ed Snoop Event Occurs Snoop Event Serviced A sse rted 1. Normal State Normal execution.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 4.2.4 Halt/Grant Snoop State — State 4 The Pentium III Xeon processor will respond to snoop phase transactions (initiated by ADS#) on the system bus while in Stop-Grant state or in Auto HALT Power Down state. When a snoop transaction is presented upon the system bus, the processor will enter the HALT/Grant Snoop state.
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Pentium® III Xeon™ Processor at 500 and 550 MHz The processor will not enter any low power states until all internal queues for the second level cache are empty. When re-entering Normal state, the processor will resume processing external cache requests as soon as new requests are encountered. 4.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 4.3.1 Processor Information ROM An electrically programmed read-only memory with information about the Pentium III Xeon processor is provided on the processor substrate. This information is permanently write-protected. Table 23 shows the data fields and formats provided in the memory. Table 23.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 23. Processor Information ROM Format (Sheet 2 of 2) Offset/Section CARTRIDGE: 32h PART NUMBERS: 38h THERMAL REF.: 70h FEATURES: 74h OTHER: 7Eh 4.3.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 4.3.3 Processor Information ROM and Scratch EEPROM Supported SMBus Transactions The Processor Information ROM responds to three SMBus packet types: current address read, random address read, and sequential read. The Scratch EEPROM responds to two additional packet types: byte write and page write. Table 24 diagrams the current address read.
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Pentium® III Xeon™ Processor at 500 and 550 MHz thermal diode is sensed and the precision A/D converter derives a single byte of thermal reference data, or a “thermal byte reading.” System management software running on the processor or on a microcontroller can acquire the data from the thermal sensor to thermally manage the system. Upper and lower thermal reference thresholds can be individually programmed for the thermal diode.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 27. Write Byte SMBus Packet S Address Write Ack Command Ack Data Ack P 1 7 bits 1 1 8 bits 1 8 bits 1 1 Table 28. Read Byte SMBus Packet S Addres Write Ack Command Ack S Addres Read Ack Data /// P 1 7 bits 1 1 8 bits 1 1 7 bits 1 1 8 bits 1 1 Table 29. Send Byte SMBus Packet S Addres Write Ack Command Ack P 1 7 bits 1 1 8 bits 1 1 Table 30.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 32.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 33. Thermal Sensor Status Register 4.3.6.4 Bit Name Function 7 (MSB) BUSY A one indicates that the device’s analog to digital converter is busy converting. 6 RESERVED Reserved for future use 5 RESERVED Reserved for future use 4 RHIGH A one indicates that the processor core thermal diode high temperature alarm has activated. 3 RLOW A one indicates that the processor core thermal diode low temperature alarm has activated.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 35. Thermal Sensor Conversion Rate Register 4.3.7 Register Contents Conversion Rate (Hz) 00h 0.0625 01h 0.125 02h 0.25 03h 0.5 04h 1 05h 2 06h 4 07h 8 08h to FF Reserved for future use SMBus Device Addressing Of the addresses broadcast across the SMBus, the memory components claim those of the form “1010XXYZb”. The “XX” and “Y” bits are used to enable the devices on the cartridge at adjacent addresses.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 36. Thermal Sensor SMBus Addressing on the Pentium ® III Xeon™ Processor Address (Hex) Upper Address1 3Xh 5Xh Slot Selec SA1 SA2 b[7:0] 0011 0 0 0011000Xb 0011 1 0 0011010Xb 0101 9Xh 8-bit Address Word on Serial Bus 0 2 0101001Xb 2 Z 0101 1 Z 0101011Xb 1001 0 1 1001100Xb 1001 1 1 1001110Xb NOTES 1. Upper address bits are decoded in conjunction with the select pins. 2.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Figure 18. Thermal Plate View 5.1 Thermal Specifications This section provides power dissipation specifications for each variation of the Pentium III Xeon processor. The thermal plate flatness is also specified for the S.E.C. cartridge. 5.1.1 Power Dissipation Table 38 provides the thermal design power dissipation for Pentium III Xeon processors.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 38. Thermal Design Power 1 Processor Core Frequency (MHz) L2 Cache Size Core Power (W) L2 Power (W) AGTL+ Power4 (W) Processor Power2 (W) Thermal Plate Power3 (W) Min TPLATE (°C) Max TPLATE (°C) Min TCOVER (°C) Max TCOVER (°C) FMB5 - 35.2 21.0 2 50.0 50.0 0 68 0 75 500 512K 28.0 12.0 2 36.0 37.0 0 75 0 75 500 1M 28.0 19.0 2 44.0 45.0 0 75 0 75 500 2M 28.0 11.6 2 36.2 37.1 0 75 0 75 550 512K 30.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 5.2 Processor Thermal Analysis 5.2.1 Thermal Solution Performance Processor cooling solutions should attach to the thermal plate. The processor cover is not designed for thermal solution attachment. The complete thermal solution must adequately control the thermal plate and cover temperatures below the maximum and above the minimum specified in Table 38.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Figure 20. Interface Agent Dispensing Areas and Thermal Plate Temperature Measurement Points 1.960 .980 NOTES 6. Interface agent suggestions: ShinEtsu* G749 or Thermoset* TC330; Dispense volume adequate to ensure required minimum area of coverage when cooling solution is attached. Areas A and C are suggested for the 512-Kbyte L2 cache product and areas A, B, and D for the 1-Mbyte and 2-Mbyte L2 cache products.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 2-Mbyte L2 cache products. Figure 20 shows the locations for TPLATE measurement directly above these transfer locations. Figure 23 shows the 4 locations for TCOVER measurement, directly above component locations on the back side of the processor substrate. Thermocouples are used to measure TPLATE and special care is required to ensure an accurate temperature measurement. Before taking any temperature measurements, the thermocouples must be calibrated.
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Pentium® III Xeon™ Processor at 500 and 550 MHz areas on the cover have been characterized and are illustrated in Figure 23. If no external heat sources are present, TCOVER thermal measurements should be made at these points. The cover is not designed for thermal solution attachment. Figure 23. Guideline Locations for Cover Temperature (TCOVER) Thermocouple Placement NOTE: 8. Four thermocouple attach locations at ±0.015".
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 40 and Table 41 provide the edge finger and SC330 connector signal definitions for Pentium III Xeon processors. The signal locations on the SC330 edge connector are to be used for signal routing, simulation and component placement on the baseboard. Figure 24. Isometric View of Pentium® III Xeon™ Processor S.E.C. Cartridge NOTES: Use of retention holes and retention indents are optional. 11.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 3.000 ± .017 2.658 ±.035 Figure 25. S.E.C.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Figure 26. S.E.C. Cartridge Retention Enabling Details (Notes follow Figure 27) .325 ± .004 5.350 ± .008 2X Ø .125 ± .002 2X .280 ± .009 6.000 58 +.015 - .
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Pentium® III Xeon™ Processor at 500 and 550 MHz Figure 27. S.E.C. Cartridge Retention Enabling Details .277 ± .174 22 P .919 ± .010 .189 2 4.840 ± .032 (FRONTSIDE HEIGHT) P 4.777 ± .036 4.836 ± .008 (BACKSIDE HEIGHT) .287 ± .016 .150 ± .010 SECTION P-P .733 ± .013 SECTION F-F NOTES 1. Maximum protrusion of the mechanical heatsink attach media into cartridge during assembly or in an installed condition not to exceed 0.160" from external face of thermal plate. 2.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 6.1 Weight The maximum weight of a Pentium III Xeon processor is approximately 500 grams. 6.2 Cartridge to Connector Mating Details The staggered edge connector layout of the Pentium III Xeon processor makes the processor susceptible to damage from hot socketing (inserting the cartridge while power is applied to the connector). Extra care should be taken to ensure hot socketing does not occur.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Figure 29. Top View of Cartridge Insertion Pressure Points Figure 30. Front View of Connector Mating Details Z Y X .168 ± .021 NOTE: 5. Retention devices for this cartridge must accommodate this cartridge “Float” relative to connector, without preload to the edge contacts in “X” and “Y” axes.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 6.3 Pentium® III Xeon™ Processor Substrate Edge Finger Signal Listing Table 40 is the Pentium III Xeon processor substrate edge finger listing in order by pin number Table 41 is the Pentium III Xeon processor substrate edge connector listing in order by pin name. Table 40. Signal Listing in Order by Pin Number (Sheet 1 of 4) Pin No. 62 Pin Name Signal Buffer Type Pin No.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 40. Signal Listing in Order by Pin Number (Sheet 2 of 4) Pin No. Datasheet Pin Name Signal Buffer Type Pin No.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 40. Signal Listing in Order by Pin Number (Sheet 3 of 4) Pin No. 64 Pin Name Signal Buffer Type Pin No.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 40. Signal Listing in Order by Pin Number (Sheet 4 of 4) Pin No. Datasheet Pin Name Signal Buffer Type Pin No.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 41. Signal Listing in Order by Pin Name (Sheet 2 of 9) Table 41. Signal Listing in Order by Pin Name (Sheet 1 of 9) Pin No. 66 Pin Name Signal Buffer Type Pin No.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 41. Signal Listing in Order by Pin Name (Sheet 3 of 9) Pin No. Pin Name Signal Buffer Type Table 41. Signal Listing in Order by Pin Name (Sheet 4 of 9) Pin No.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 41. Signal Listing in Order by Pin Name (Sheet 5 of 9) Pin No. A83 68 Pin Name RESERVED_A83 Signal Buffer Type Table 41. Signal Listing in Order by Pin Name (Sheet 6 of 9) Pin No.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 41. Signal Listing in Order by Pin Name (Sheet 7 of 9) Pin No. Pin Name Signal Buffer Type Table 41. Signal Listing in Order by Pin Name (Sheet 8 of 9) Pin No.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 41. Signal Listing in Order by Pin Name (Sheet 9 of 9) Pin No.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 7.0 Boxed Processor Specifications 7.1 Introduction The Pentium III Xeon processor is also offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and off-the-shelf components. The boxed Pentium III Xeon processor is supplied with an attached passive heatsink.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Figure 32.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Figure 33. Front View Space Requirements for the Boxed Processor D C 7.2.1 Boxed Processor Heatsink Dimensions Table 42. Boxed Processor Heatsink Dimensions Fig. Ref. Label 7.2.2 Dimensions (Inches) Min Typ A Heatsink Depth (off heatsink attach point) 1.025 B Heatsink Height (above baseboard 0.626 C Heatsink Height (see front view) 4.235 D Heatsink Width (see front view) 5.
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Pentium® III Xeon™ Processor at 500 and 550 MHz system integrators should include a retention mechanism and appropriate installation instructions. The boxed Pentium III Xeon processor does not require additional heatsink supports. Heatsink supports will not ship with the boxed Pentium III Xeon processor. 7.3 Thermal Specifications This section describes the cooling requirements of the heatsink solution utilized by the boxed processor. 7.3.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Figure 34. Front Views of the Boxed Processor with Attached Auxiliary Fan (Not Included with Boxed Processor) Figure 35. Front View of Boxed Processor Heatsink with Fan Attach Features (Fan Not Included) 1.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Figure 36. Cross-sectional View of Grommet Attach Features in the Heatsink (Grommet Shown) 7.3.2.1 Clearance Recommendations for Auxiliary Fan If an auxiliary fan is used, clearance must be provided in front of the boxed processor passive heatsink to accommodate the mechanical and airflow clearance requirements of the fan and mounting hardware.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Figure 38. Front View Space Recommendations for the Auxiliary Fan 7.3.2.2 Fan Power Recommendations for Auxiliary Fan To facilitate power to the auxiliary fan and provide fan monitoring, a fan-sense capable power header may be provided on the baseboard near every processor that may need an auxiliary fan. Although the boxed processor does not ship with an auxiliary fan, it is highly recommended that a power header be provided.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 43. Fan/Heatsink Power and Signal Specifications Description +12 V: 12 volt fan power supply Min Typ 7V 12 V IC: Fan current draw SENSE: SENSE frequency (baseboard should pull this pin up to appropriate VCC with resistor (typically 12 kΩ) 7.3.2.3 Max 13.
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Pentium® III Xeon™ Processor at 500 and 550 MHz debug interface. Due to the nature of an ITP, the processor may be controlled without affecting any high speed signals. This ensures that the system can operate at full speed with an ITP attached. Intel will use an ITP for internal debug and system validation and recommends that all Pentium III Xeon processor-based system designs include a debug port.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 8.1.3 Debug Port Signal Descriptions Table 44 describes the debug port signals and provides the pin assignment. Table 44. Debug Port Pinout Description and Requirements Name RESET# Pin 1 1 (Sheet 1 of 3) Description Specification Requirement Reset signal from MP cluster to ITP. Terminate2 signal properly at the debug port Debug port must be at the end of the signal trace DBRESET# 3 Allows ITP to reset entire target system.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 44. Debug Port Pinout Description and Requirements Name TDO Pin 10 Description Test data output signal from last component in boundary scan chain of MP cluster to ITP; test output is read serially. 1 (Sheet 2 of 3) Specification Requirement Notes Add 150W pull-up resistor (to VCCTAP) Operates synchronously with TCK. Each Pentium III Xeo processor have a 25W driver.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 44. Debug Port Pinout Description and Requirements Name PRDY3# Pin 30 (Sheet 3 of 3) Specification Requirement Description PRDY3# signal fro ITP to P3. 1 Notes Terminate2 signal properly at the debug port Debug port must be at the end of the signal trace BCLK 29 Bus clock from the MP cluster. Use a separate driver to drive signal to the debug port. Must be connected to support future steppings of the Pentium III Xeon processors.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 8.1.4.1 General Signal Quality Notes Signals from the debug port are fed to the system from an ITP via a buffer board and a cable. If system signals routed to the debug port (i.e., TDO, PRDY[x]# and RESET#) are used elsewhere in the system, then dedicated drivers should be used to isolate the signals from reflections coming from the end of this cable.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Due to the number of loads on the TCK signal, special care should be taken when routing this signal on the baseboard. Poor routing can lead to multiple clocking of some agents on the debug chain. This causes information to be lost through the chain and can result in bad commands being issued to some agents on the chain. The suggested routing scheme is to drive each agent's TCK signals individually from a buffer device.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Note: The buffer rise and fall edge rates should NOT be FASTER than 3ns. Edge rates faster than this in the system can contribute to signal reflections which endanger ITP compatibility with the target system. A low voltage buffer capable of drivin g 2.5V outputs such asan 74LVQ244 is suggested to eliminate the need for attenuation. Simulation should be performed to verify that the edge rates of the buffer chosen are not too fast. The pull-up resistor to 2.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 8.2 Integration Tool (Logic Analyzer) Considerations Target platforms must be designed to allow for the mechanical keep-out zones. These keep-outs allow a logic analyzer interface to be plugged in between the processor slots. Intel now uses only third party solutions for logic analyzers. The companies that Intel has enabled at the time of publication have been Hewlett-Packard* and Tektronix*.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 9.1.3 ADS# (I/O) The ADS# (Address Strobe) signal is asserted to indicate the validity of the transaction address on the A[35:03]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. This signal must connect the appropriate pins on all Pentium III Xeon processor system bus agents. 9.1.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 9.1.8 BINIT# (I/O) The BINIT# (Bus Initialization) signal may be observed and driven by all Pentium III Xeon processor system bus agents, and if used must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future information.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 45. BR[3:0]# Signals Rotating Interconnect, 4-Way System Bus Signal Agent 0 Pins Agent 1 Pins Agent 2 Pins Agent 3 Pins BREQ0# BR0# BR3# BR2# BR1# BREQ1# BR1# BR0# BR3# BR2# BREQ2# BR2# BR1# BR0# BR3# BREQ3# BR3# BR2# BR1# BR0# Table 46 gives the interconnect between the processor and bus signals for a 2-way system. Table 46.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 9.1.16 DBSY# (I/O) The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on the Pentium III Xeon processor system bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on all Pentium III Xeon processor system bus agents. 9.1.
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Pentium® III Xeon™ Processor at 500 and 550 MHz On the active-to-inactive transition of RESET#, each processor samples FLUSH# to determine its power-on configuration. See Pentium® II Processor Developer’s Manual for details. 9.1.
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Pentium® III Xeon™ Processor at 500 and 550 MHz During active RESET#, the Pentium III Xeon processor begins sampling the A20M#, IGNNE# , and LINT[1:0] values to determine the ratio of core-clock frequency to bus-clock frequency. See Table 1. On the active-to-inactive transition of RESET#, the Pentium III Xeon processor latches these signals and freezes the frequency ratio internally. System logic must then release these signals for normal operation. 9.1.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 9.1.31 L2_SENSE The L2_SENSE pin is connected to the VCC_L2 power plane on the substrate. 9.1.32 NMI - See LINT1 9.1.33 PICCLK (I) The PICCLK (APIC Clock) signal is an input clock to the processor and core logic or I/O APIC which is required for operation of all processors, core logic, and I/O APIC components on the APIC bus. During FRC mode operation, PICCLK must be 1/4 of (and synchronous to) BCLK. 9.1.
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Pentium® III Xeon™ Processor at 500 and 550 MHz PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. It must also meet the minimum pulse width specification in Table 11 and be followed by a 1 m s RESET# pulse. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. The PWRGOOD signal does not need to be synchronized for FRC operation.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 9.1.42 RP# (I/O) The RP# (Request Parity) signal is driven by the request initiator, and provides parity protection on ADS# and REQ[4:0]#. It must connect the appropriate pins of all Pentium III Xeon processor system bus agents. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This definition allows parity to be high when all covered signals are high. 9.1.
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Pentium® III Xeon™ Processor at 500 and 550 MHz signals to a Hi-Z state would cause ambiguity in the memory device address decode, possibly resulting in the devices not responding, thus timing out or hanging the SMBus. As before, the “Z” bit is the read/write bit for the serial bus transaction. For more information on the usage of these pins, see Section 4.3.7. 9.1.46 SELFSB[1:0] (I/O) Pentium III Xeon processors do not have a selectable system bus speed option.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 9.1.52 STPCLK# (I) The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a low power Stop Grant state. The processor issues a Stop Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop Grant state.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 9.1.59 TMS (I) The TMS (Test Mode Select) signal is a TAP support signal used by debug tools. 9.1.60 TRDY# (I) The TRDY# (Target Ready) signal is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all Pentium III Xeon processor system bus agents. 9.1.61 TRST# (I) The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 49.
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Pentium® III Xeon™ Processor at 500 and 550 MHz Table 50.
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Pentium® III Xeon™ Processor at 500 and 550 MHz 1.0 1.1 1.2 Introduction.........................................................................................................................9 Terminology .......................................................................................................... 9 1.1.1 S.E.C. Cartridge Terminology................................................................ 10 References .................................................................................
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Pentium® III Xeon™ Processor at 500 and 550 MHz 4.3.7 5.0 5.1 5.2 6.0 6.1 6.2 6.3 7.0 7.1 7.2 7.3 8.0 8.1 8.2 9.0 9.1 102 4.3.6.1 Thermal Reference Registers....................................................46 4.3.6.2 Thermal Limit Registers.............................................................46 4.3.6.3 Status Register ..........................................................................46 4.3.6.4 Configuration Register ...............................................................
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Pentium® III Xeon™ Processor at 500 and 550 MHz 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 9.1.7 9.1.8 9.1.9 9.1.10 9.1.11 9.1.12 9.1.13 9.1.14 9.1.15 9.1.16 9.1.17 9.1.18 9.1.19 9.1.20 9.1.21 9.1.22 9.1.23 9.1.24 9.1.25 9.1.26 9.1.27 9.1.28 9.1.29 9.1.30 9.1.31 9.1.32 9.1.33 9.1.34 9.1.35 9.1.36 9.1.37 9.1.38 9.1.39 9.1.40 9.1.41 9.1.42 9.1.43 9.1.44 9.1.45 9.1.46 9.1.47 9.1.48 9.1.49 9.1.50 9.1.51 Datasheet A20M# (I) ...............................................................................................
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Pentium® III Xeon™ Processor at 500 and 550 MHz 9.2 104 9.1.52 STPCLK# (I) ...........................................................................................97 9.1.53 TCK (I) ....................................................................................................97 9.1.54 TDI (I) .....................................................................................................97 9.1.55 TDO (O) ........................................................................................
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Pentium® III Xeon™ Processor at 500 and 550 MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Timing Diagram of Clock Ratio Signals .............................................................. 15 Logical Schematic for Clock Ratio Pin Sharing .................................................. 15 I-V Curve for nMOS Device ................................................................................
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Pentium® III Xeon™ Processor at 500 and 550 MHz 106 Datasheet
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Pentium® III Xeon™ Processor at 500 and 550 MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Core Frequency to System Bus Multiplier Configuration.................................... 14 Core and L2 Voltage Identification Definition 1, 2...................................................................16 Pentium® III Xeon™ Processor System Bus Pin Groups ...................................
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Pentium® III Xeon™ Processor at 500 and 550 MHz 51 108 I/O Signals (Multiple Driver)...............................................................................
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UNITED STATES, Intel Corporation 2200 Mission College Blvd., P.O. Box 58119, Santa Clara, CA 95052-8119 Tel: +1 408 765-8080 JAPAN, Intel Japan K.K. 5-6 Tokodai, Tsukuba-shi, Ibaraki-ken 300-26 Tel: + 81-29847-8522 FRANCE, Intel Corporation S.A.R.L. 1, Quai de Grenelle, 75015 Paris Tel: +33 1-45717171 UNITED KINGDOM, Intel Corporation (U.K.) Ltd.