Datasheet

Pentium
®
III Xeon™ Processor at 500 and 550 MHz
88
Datasheet
9.1.8 BINIT# (I/O)
The BINIT# (Bus Initialization) signal may be observed and driven by all Pentium
III
Xeon
processor system bus agents, and if used must connect the appropriate pins of all such agents. If the
BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal any bus
condition that prevents reliable future information.
If BINIT# observation is enabled during power-on configuration, and BINIT# is sampled asserted,
all bus state machines are reset and any data which was in transit is lost. All agents reset their
rotating ID for bus arbitration to the state after reset, and internal count information is lost. The L1
and L2 caches are not affected.
If BINIT# observation is disabled during power-on configuration, a central agent may handle an
assertion of BINIT# as appropriate to the Machine Check Architecture (MCA) of the system.
9.1.9 BNR# (I/O)
The BNR# (Block Next Request) signal is used to assert a bus stall by any bus agent who is unable
to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new
transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a wire-OR signal
which must connect the appropriate pins of all Pentium
III
Xeon processor system bus agents. In
order to avoid wire-OR glitches associated with simultaneous edge transitions driven by multiple
drivers, BNR# is activated on specific clock edges and sampled on specific clock edges.
9.1.10 BP[3:2]# (I/O)
The BP[3:2]# (Breakpoint) signals are outputs from the processor that indicate the status of
breakpoints.
9.1.11 BPM[1:0]# (I/O)
The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance monitor signals.
They are outputs from the processor which indicate the status of breakpoints and programmable
counters used for monitoring processor performance.
9.1.12 BPRI# (I)
The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the Pentium
III
Xeon
processor system bus. It must connect the appropriate pins of all Pentium
III
Xeon processor system
bus agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to
stop issuing new requests, unless such requests are part of an ongoing locked operation. The
priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by
deasserting BPRI#.
9.1.13 BR0# (I/O), BR[3:1]# (I)
The BR[3:1]# (Bus Request) pins drive the BREQ[3:0]# signals on the system. The BR[3:0]# pins
are interconnected in a rotating manner to other processors’ BR[3:0]# pins. Table 45 gives the
rotating interconnect between the processor and bus signals for 4-way systems.