Datasheet

Pentium
®
III Xeon™ Processor at 500 and 550 MHz
Datasheet
9
1.0 Introduction
The Pentium
III
Xeon processor is a follow-on to the Pentium Pro and Pentium
®
II
Xeon
processors. The Pentium
III
Xeon processor, like the Pentium Pro and Pentium
II
Xeon processors,
implements a Dynamic Execution micro-architecture — a unique combination of multiple branch
prediction, data flow analysis, and speculative execution. This enables Pentium
III
Xeon processors
to deliver higher performance than the Pentium
®
processor, while maintaining binary compatibility
with all previous
Intel Architecture
processors. The Pentium III Xeon processor is available in
512K, 1MB, and 2MB L2 cache options.
The Pentium
III
Xeon processor, like the Pentium
II
Xeon processor, executes MMX

technology
instructions for enhanced media and communication performance. In addition, the Pentium
®
III
processor executes Streaming SIMD Extensions for enhanced floating point and 3-D application
performance.The Pentium
III
Xeon processor also utilizes the Single Edge Contact Cartridge
(S.E.C.C.) package technology first introduced on the Pentium
®
II
processor. This packaging
technology allows Pentium
III
Xeon processors to implement the Dual Independent Bus
Architecture and have up to 2-MBytes of level 2 cache. Like the Pentium Pro and Pentium
II
Xeon
processors, level 2 cache communication occurs at the full speed of the processor core. The
Pentium
III
Xeon processor extends the concept of processor identification with the addition of a
processor serial number. Refer to the
Intel
®
Processor Serial Number
for more detailed
information on the implementation of the Intel processor serial number. A significant feature of the
Pentium
III
Xeon processor, from a system perspective, is the built-in direct multiprocessing
support. For systems with up to four processors, it is important to consider the additional power
burdens and signal integrity issues of supporting multiple loads on a high-speed bus. The Pentium
III
Xeon processor supports both uniprocessor and multiprocessor implementations with up to four
processor on each local processor bus, or
system bus
.
The Pentium
III
Xeon processor system bus operates using GTL+ signaling levels with a new type
of buffer utilizing active negation and multiple terminations. This new bus logic is called
Assisted
Gunning Transistor Logic,
or
AGTL+.
The Pentium
III
Xeon processors also deviate from the
Pentium Pro processor in implementing an S.E.C. cartridge package supported by the 330-Contact
Slot Connector (SC330). (See Section 6.0 for the processor mechanical specifications.) This
document provides information to allow the user to design a system using Pentium
III
Xeon
processors.
1.1 Terminology
In this document, a ‘#’ symbol after a signal name refers to an active low signal. This means that a
signal is in the active state (based on the name of the signal) when driven to a low level. For
example, when FLUSH# is low, a flush has been requested. When NMI is high, a nonmaskable
interrupt has occurred. In the case of lines where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal
is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D [3:0] # = ‘LHLH’ also refers
to a hex ‘A’ (H= High logic level, L= Low logic level).
The term ‘system bus’ refers to the interface between the processor, system core logic and other
bus agents. The system bus is a multiprocessing interface to processors, memory and I/O. The term
‘cache bus’ refers to the interface between the processor and the L2 cache. The cache bus does
NOT connect to the system bus, and is not accessible by other agents on the system bus. Cache
coherency is maintained with other agents on the system bus through the MESI cache protocol as
supported by the HIT# and HITM# bus signals.