Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Datasheet Revision 8 Product Features ■ ■ ■ ■ ■ ■ ■ Available in 1.13 GHz, 1B GHz, 933, 866, 800EB, 733, 667, 600EB, and 533EB MHz for a 133 MHz system bus Available in 1.
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Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Contents 1.0 Introduction .................................................................................................................. 8 1.1 1.2 2.0 Electrical Specifications ........................................................................................13 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 3.0 Processor System Bus and VREF ........................................................................
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Guidelines ........................................................................................................... 54 3.4.1 Overshoot/Undershoot Guidelines ......................................................... 54 3.4.2 Ringback Specification........................................................................... 55 3.4.3 Settling Limit Guideline .......................................................................... 55 4.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Datasheet Second Level (L2) Cache Implementation ........................................................... 8 AGTL+/AGTL Bus Topology in a Uniprocessor Configuration ............................14 AGTL+/AGTL Bus Topology in a Dual-Processor Configuration ........................14 Stop Clock State Machine .......................
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 6 Processor Identification....................................................................................... 10 Voltage Identification Definition........................................................................... 21 System Bus Signal Groups 1 ...................................................................
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 41 42 43 44 45 46 Datasheet Fan Heatsink Power and Signal Specifications...................................................84 Signal Description ...............................................................................................85 Output Signals.....................................................................................................92 Input Signals...................................................................
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 1.0 Introduction The Intel® Pentium® III processor for the PGA370 socket is the next member of the P6 family, in the Intel IA-32 processor line and hereafter will be referred to as the “Pentium III processor”, or simply “the processor”. The processor uses the same core and offers the same performance as the Pentium III processor for the SC242 connector, but utilizes a package technology called flip-chip pin grid array, or FC-PGA.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 1.1 Terminology In this document, a ‘#’ symbol after a signal name refers to an active low signal. This means that a signal is in the active state (based on the name of the signal) when driven to a low level. For example, when FLUSH# is low, a flush has been requested. When NMI is high, a nonmaskable interrupt has occurred.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz • SC242 - The 242-contact slot connector (previously referred to as slot 1 connector) that the S.E.C.C. and S.E.C.C. 2 plug into, just as the Intel® Pentium® Pro processor uses socket 8. The cache and L2 cache are an industry designated names. 1.1.2 Processor Naming Convention A letter(s) is added to certain processors (e.g., 600EB MHz) when the core frequency alone may not uniquely identify the processor.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 1.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz NOTES: 1. Unless otherwise noted, this reference material can be found on the Intel Developer’s Website located at http://developer.intel.com. 2. For a complete listing of Pentium III processor reference material, please refer to the Intel Developer’s Website at http://developer.intel.com/design/PentiumIII/. 3. This material is available through an Intel field sales representative.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 2.0 Electrical Specifications 2.1 Processor System Bus and VREF The Pentium III processor signals use a variation of the low voltage Gunning Transceiver Logic (GTL) signaling technology. The Pentium Pro processor system bus specification is similar to the GTL specification, but was enhanced to provide larger noise margins and reduced ringing.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz system with a heavily loaded AGTL+ bus, especially for systems using a single set of termination resistors (i.e., those on the processor die). Such designs will not match the solution space allowed for by installation of termination resistors on the baseboard. Figure 2. AGTL+/AGTL Bus Topology in a Uniprocessor Configuration Processor Chipset Figure 3. AGTL+/AGTL Bus Topology in a Dual-Processor Configuration Processor 2.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Figure 4. Stop Clock State Machine HA LT Instruction and HA LT B us C ycle G enerated 2. Au to HAL T P o w er D ow n S tate B CLK running. S noops and interrupts allowed. IN IT#, B IN IT #, IN T R , S M I#, R E S E T # , NMI 1. No rm al S tate N orm al execution. S T P CLK # A sserted S noop E vent O ccurs S noop E vent S erviced 4. HAL T/G rant S no op S tate B CLK running. S ervice snoops to caches.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor returns execution to the HALT state. 2.2.3 Stop-Grant State—State 3 The Stop-Grant state on the processor is entered when the STPCLK# signal is asserted.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep state, by stopping the BCLK input (see Section 2.2.6). Once in the Sleep or Deep Sleep states, the SLP# pin can be deasserted if another asynchronous system bus event occurs. The SLP# pin has a minimum assertion of one BCLK period. 2.2.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz (1.5 V/1.25 V) are used to provide an AGTL+/AGTL termination voltage to the processor, and the VREF inputs are used as the AGTL+/AGTL reference voltage for the processor. Note that not all VTT inputs must be connected to the VTT supply. Refer to Section 5.4 for more details. On the motherboard, all VCCCORE pins must be connected to a voltage island (an island is a portion of a power plane that has been divided, or an entire plane).
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 2.4 Decoupling Guidelines Due to the large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. The fluctuations can cause voltages on power planes to sag below their nominal values if bulk decoupling is not adequate.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Note: References to BCLK throughout this document will also imply to its complement signal, BCLK#, in differential implementations and when noted otherwise. For a differential clock input, all AGTL system bus timing parameters are specified with respect to the crossing point of the rising edge of the BCLK input and the falling edge of the BCLK# input. See the P6 Family of Processors Hardware Developer's Manual for further details.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 2. Voltage Identification Definition 1, 2 VID3 VID2 VID1 VID0 VccCORE 1 1 1 1 1.30 1 1 1 0 1.35 1 1 0 1 1.40 1 1 0 0 1.45 1 0 1 1 1.50 1 0 1 0 1.55 1 0 0 1 1.603 1 0 0 0 1.653 0 1 1 1 1.703 0 1 1 0 1.753 0 1 0 1 1.80 3 0 1 0 0 1.85 3 0 0 1 1 1.90 3 0 0 1 0 1.95 3 0 0 0 1 2.00 3 0 0 0 0 2.05 3 1 1 1 1 No Core NOTES: 1.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 2.7 Processor System Bus Unused Pins All RESERVED pins must remain unconnected unless specifically noted. Connection of these pins to VCCCORE, VREF, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Section 5.4 for a pin listing of the processor and the location of each RESERVED pin.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz The groups and the signals contained within each group are shown in Table 3 and Table 4. Refer to Section 7.0 for a description of these signals. Table 3.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 4. System Bus Signal Groups (AGTL)1 (Sheet 2 of 2) Group Name System Bus Clock10, 12 Signals BCLK, BCLK0# (1.25 V/2.5 V) APIC Clock (2.0 V) PICCLK11 APIC I/O3 PICD[1:0] Power/Other5 BSEL[1:0], CLKREF10, CPUPRES#, EDGCTRL, PLL[2:1], RESET2#, SLEWCTRL, THERMDN, THERMDP, RTTCTRL8, VCOREDET, VID[3:0], VCC1.5, VCC2.5, VCCCMOS, VCCCORE, VREF, VSS, VTT, Reserved NOTES: 1. See Section 7.0 for information on the these signals. 2.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 2.8.2 System Bus Frequency Select Signals (BSEL[1:0]) These signals are used to select the system bus frequency for the processor. The BSEL signals are also used by the chipset and system bus clock generator. Table 5 defines the possible combinations of the signals and the frequency associated with each combination. The frequency selection is determined by the processor(s) and driven out to the chipset and clock generator.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 5. 2.9 Frequency Select Truth Table for BSEL[1:0] BSEL1 BSEL0 Frequency 0 0 66 MHz (unsupported) 0 1 100 MHz 1 0 Reserved 1 1 133 MHz Maximum Ratings Table 6 contains processor stress ratings only. Functional operation at the absolute maximum and minimum is not implied nor guaranteed. The processor should not receive a clock while subjected to these conditions.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 2.10 Processor DC Specifications The processor DC specifications in this section are defined at the PGA370 socket pins (bottom side of the motherboard). See Section 7.0 for the processor signal descriptions and Section 5.4 for the signal listings. Most of the signals on the processor system bus are in the AGTL+ (AGTL) signal group. These signals are specified to be terminated to 1.5 V for AGTL+ or 1.25 V for AGTL.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 7. Voltage and Current Specifications 1, 2 (Sheet 1 of 5) Processor Symbol Parameter Unit Notes 0x681 1.60 3,4 0x683 1.60 3,4 0x686 n/a 3,4 0x681 1.65 3,4 0x683 1.65 3,4 0x686 n/a 3,4 0x681 1.60 3,4 0x683 1.65 3,4 0x686 1.70 3,4 0x681 1.65 3,4 0x683 1.65 3,4 0x686 1.70 3,4 0x68A 1.75 3,4 0x681 1.65 3,4 0x683 1.65 3,4 0x686 1.70 3,4 0x681 1.65 0x683 1.65 3,4 0x686 1.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 7. Voltage and Current Specifications 1, 2 (Sheet 2 of 5) Processor Symbol Parameter Unit Notes 0x681 1.65 3,4 0x683 1.65 3,4 0x686 1.70 3,4 0x681 1.65 3,4 0x683 1.65 3,4 0x686 1.70 3,4 0x68A 1.75 3,4 0x681 1.65 3,4 0x683 1.65 3,4 0x686 1.70 3,4 0x68A 1.75 3,4 0x681 1.65 3,4 0x683 1.65 3,4 0x686 1.70 0x68A 1.75 3,4 0x686 1.70 3,4 866 MHz 900 MHz 933 MHz 1 GHz V 3,4 0x68A 1.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 7. Voltage and Current Specifications 1, 2 (Sheet 3 of 5) Processor Symbol Min Typ Max Unit Notes Static AGTL+ bus termination voltage 1.455 1.50 1.545 V 1.5 ±3% 5,16 Static AGTL bus termination voltage 1.213 1.25 1.288 V 1.25 ±3% 5,16,17 Transient AGTL+ bus termination voltage 1.365 1.50 1.635 V 1.5 ±9% 5 Transient AGTL bus termination voltage 1.138 1.25 1.363 V 1.25 ±9% 5,17 Vcc1.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 7. Voltage and Current Specifications 1, 2 (Sheet 4 of 5) Processor Symbol Parameter Max Unit Notes 500E MHz 0x683 10.0 3, 8, 9 0x686 12.0 3, 8, 9 0x68A 12.6 3, 8, 9 600EB MHz 0x686 12.0 3, 8, 9 650 MHz 0x686 13.0 3, 8, 9 667B MHz 0x686 13.3 3, 8, 9 700 MHz 0x686 14.0 3, 8, 9 0x68A 14.8 3, 8, 9 733B MHz 0x686 14.6 3, 8, 9 0x68A 15.4 3, 8, 9 0x686 15.0 3, 8, 9 0x68A 15.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 7. Voltage and Current Specifications 1, 2 (Sheet 5 of 5) Processor Symbol Parameter Core Freq Min Typ Max Unit Notes CPUID ICCCMOS ICC for VccCMOS 250 mA ICLKREF CLKREF voltage supply current 60 µA IVTT Termination voltage supply current 2.7 A 10 ISGnt ICC Stop-Grant for processor core 6.9 A 8, 11 ISLP ICC Sleep for processor core 6.9 A 8 IDSLP ICC Deep Sleep for processor core 6.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 18.This specification only applies to 1B GHz S-spec #: SL4WM. This part has a VID request of 1.70 V, however the processor should be supplied 1.76 V at the PGA Vcc pin by the Voltage Regulator Circuit or VRM. 19.This specification applies only to 1B GHz S-spec #: SL4WM. This value is 60 mV offset from the standard specification and more at the Minimum specification. These tolerances are measured from a 1.70 V base, while Vcc supplied is 1.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 8. Table 9. PL Slew Rate Data (23A) (Sheet 2 of 2) Time (µs) ICC (A) 4.5 21.88 5 22.01 AGTL / AGTL+ Signal Groups DC Specifications 1 Symbol VIL Parameter Min Max Unit Notes Input Low Voltage –0.150 VREF - 0.200 V 6 VREF + 0.200 VIH Input High Voltage VTT V 2, 3, 6 Ron Buffer On Resistance 16.67 Ω 5 IL Leakage Current for inputs, outputs, and I/O ±100 µA 4 NOTES: 1.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 11. Non-AGTL Signal Group DC Specifications 1 Symbol Parameter Min Max Unit Notes -0.150 VCMOS_REF 0.300 V 7, 8 VIL1.5 Input Low Voltage VIL2.5 Input Low Voltage -0.58 0.700 V 4, 6 VIH1.5 Input High Voltage VCMOS_REF + 0.200 1.5 V 5, 7 VIH2.5 Input High Voltage 2.000 3.18 V 4, 6 VOL Output Low Voltage 0.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 2.11 AGTL / AGTL+ System Bus Specifications It is recommended that the AGTL+ bus be routed in a daisy-chain fashion with termination resistors to VTT. These termination resistors are placed electrically between the ends of the signal traces and the VTT voltage supply and generally are chosen to approximate the system platform impedance.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 2.12 System Bus AC Specifications The processor system bus timings specified in this section are defined at the socket pins on the bottom of the motherboard. Unless otherwise specified, timings are tested at the processor pins during manufacturing. Timings at the processor pins are specified by design characterization. See Section 7.0 for the processor signal definitions.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 3. Not 100% tested. Specified by design characterization as a clock driver requirement. 4. The internal core clock frequency is derived from the processor system bus clock. The system bus clock to core clock ratio is determined during initialization. Individual processors will only operate at their specified system bus frequency, either 100 MHz or 133 MHz, not both. 5. The BCLK period allows a +0.5 ns tolerance for clock driver variation.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 16. System Bus AC Specifications (AGTL+ or AGTL Signal Group)1, 2, 3, 13 T# Parameter T7: AGTL+ Output Valid Delay Min Max Unit 0.40 3.25 Figure Notes ns 11 4, 10, 11 1.20 ns 12 5, 6, 7, 10 0.95 ns 12 5, 6, 7, 11, 12 T9: AGTL+ Input Hold Time 1.00 ns 12 8, 10 T10: RESET# Pulse Width 1.00 ms 13 6, 9, 10 T8: AGTL+ Input Setup Time NOTES: 1.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 17. System Bus AC Specifications (CMOS Signal Group) 1, 2, 3, 4 T# Parameter Min Max Unit Figure T14: CMOS Input Pulse Width, except PWRGOOD 2 BCLKs 11 T15: PWRGOOD Inactive Pulse Width 10 BCLKs 11, 14 Notes Active and Inactive states 5 NOTES: 1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies 2. These specifications are tested during manufacturing. 3.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 1. All signals, during their invalid states, must be guarded against spurious levels from effecting the platform during processor power-up sequence. 2. Configuration Input signals include: A[14:5], BR0#, BR1#, INIT#. For timing of these signals, please refer to Table 17 and Figure 13. Note: For Figure 9 through Figure 15, the following apply: 1. Figure 9 through Figure 15 are to be used in conjunction with Table 14 through Table 20. 2.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Figure 10. BCLK, PICCLK, and TCK Generic Clock Waveform Tp Th Vih diff Vringback (rise) V2 0V V3 V1 Vringback (fall) Vil diff Tr Tf Th Tl Tp V1 = = = = = = T5, T25, T34, (Rise Tim e) Tf Tl Tr T6, T26, T35, (Fall Tim e) T3, T23, T32, (High Tim e) T4, T24, T33, (Low Tim e) T1, T22, T31 (BC LK, TCK, PIC CLK Period) B CLK is referenced to 0.30V (D ifferential M ode), 0.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Figure 12. System Bus Setup and Hold Timings BCLK# VCross BCLK Ts V Th Valid VCross = Crossing point of BLCK and BCLK# Ts = T8, T12, T27 (Setup Time) NOTE: Single-Ended clock uses BCLK only, Differential clock uses BCLK and BCLK# Th = T9, T13, T28 (Hold Time) V = Vref for AGTL signal group; 0.75V for APIC and TAP signal groups Figure 13.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Figure 14.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Figure 15.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 3.0 Signal Quality Specifications Signals driven on the processor system bus should meet signal quality specifications to ensure that the components read data properly and to ensure that incoming signals do not affect the long term reliability of the component. Specifications are provided for simulation at the processor pins.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the BCLK/PICCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This specification is an absolute value. Figure 16. BCLK, PICCLK Generic Clock Waveform at the Processor Pins V3 V4 V2 V1 V5 V3 3.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 6. Intel recommends simulations not exceed a ringback value of VREF ±200 mV to allow margin for other sources of system noise. 7. A negative value for ρ indicates that the amplitude of ringback is above VREF. (i.e., φ = -100 mV specifies the signal cannot ringback below VREF + 100 mV). 8. φ and ρ: are measured relative to VREF. α: is measured relative to VREF + 200 mV. Figure 17.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 3.3.2 Overshoot/Undershoot Magnitude Magnitude describes the maximum potential difference between a signal and its voltage reference level, VSS (overshoot) and VTT (undershoot). While overshoot can be measured relative to VSS using one probe (probe to signal and GND lead to VSS), undershoot must be measured relative to VTT. This could be accomplished by simultaneously measuring the VTT plane while measuring the signal undershoot.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz just meets the pulse duration for a specific magnitude where the AF < 1, means that there can be NO other overshoot/undershoot events, even of lesser magnitude (note that if AF = 1, then the event occurs at all times and no other events can occur). 3.3.5 Note: Activity factor for AGTL+ signals is referenced to BCLK frequency. Note: Activity factor for CMOS signals is referenced to PICCLK frequency.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 3.3.6 Determining if a System Meets the Overshoot/Undershoot Specifications The overshoot/undershoot specifications listed in the following tables specify the allowable overshoot/undershoot for a single overshoot/undershoot event. However most systems will have multiple overshoot and/or undershoot events that each have their own set of parameters (duration, AF and magnitude).
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 26. 133 MHz AGTL+/AGTL Signal Group Overshoot/Undershoot Tolerance 1, 2 Maximum Pulse Duration at Tj = 80 °C (ns) Maximum Pulse Duration at Tj = 85 °C (ns) AF = 0.01 AF = 0.1 AF = 1 AF = 0.01 AF = 0.1 AF = 1 2.18 V 15 1.9 0.19 14 1.4 0.14 2.13 V 15 3.7 0.37 15 2.4 0.24 2.08 V 15 6.8 0.68 15 4.6 0.46 2.03 V 15 12.5 1.25 15 8.6 0.84 1.98 V 15 15 2.28 15 15 1.5 1.93 V 15 15 4.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Figure 18. Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform Time Dependent Overshoot 2.18V 2.08V 1.98V 1.88V 1.635V VTT Converted Undershoot Waveform Max Overshoot Magnitude Undershoot Magnitude Vss Overshoot = Signal - Vss Magnitude Undershoot = VTT - Signal Magnitude Time Dependent Undershoot Figure 19. Maximum Acceptable AGTL Overshoot/Undershoot Waveform Time dependent Overshoot .1ns .3ns 1.78V Max 1.62V 1.47V 1.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 3.4 Non-AGTL+ (Non-AGTL) Signal Quality Specifications and Measurement Guidelines There are three signal quality parameters defined for non-AGTL+ signals: overshoot/undershoot, ringback, and settling limit. All three signal quality parameters are shown in Figure 20 for the nonAGTL+ signal group. Figure 20.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 3.4.2 Ringback Specification Ringback refers to the amount of reflection seen after a signal has switched. The ringback specification is the voltage that the signal rings back to after achieving its maximum absolute value. See Figure 20 for an illustration of ringback. Excessive ringback can cause false signal detection or extend the propagation delay. The ringback specification applies to the input pin of each receiving agent.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.10 GHz 4.0 Thermal Specifications and Design Considerations This chapter provides needed data for designing a thermal solution. However, for the correct thermal measuring processes, refer to AP-905, Intel® Pentium® III Processor Thermal Design Guidelines (Document Number 245087). The Pentium III processor uses flip chip pin grid array packaging technology and has a junction (Tjunction) or case temperature (Tcase) specified. 4.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.10 GHz 2. Thermal Design Power (TDP) represents the maximum amount of power the thermal solution is required to dissipate. The thermal solution should be designed to dissipate the TDP power without exceeding the maximum Tjunction specification. 3. TDP does not represent the power delivery and voltage regulation requirements for the processor. Refer to Table 6 for voltage regulation and electrical specifications. 4.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.10 GHz Figure 21. Processor Functional Die Layout for FC-PGA C: Cache Area Product Label A: Die Area Pin 1 B: Core Area (~63% of die area) Table 32. Processor Functional Die Layout for FC-PGA 4.3 CPUID A: Die Area (cm2) B: Core Area (cm2) C: Cache Area (cm2) 0683H 1.046 0.726 0.320 0686H 0.900 0.642 0.258 068AH 0.947 0.642 0.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.10 GHz Table 33. Thermal Diode Parameters1 Symbol Parameter Min Typ Ifw Forward Bias Current 5 n Diode Ideality Factor 1.0057 1.0080 Max Unit Notes 300 µA 1 1.0125 2, 3, 4 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Characterized at 100 ° C with a forward bias current of 5 µA–300 µA. 3.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 5.0 Mechanical Specifications The Pentium III processor uses a FC-PGA and FC-PGA2 package technology. Mechanical specifications for the processor are given in this section. FC-PGA2 contains an Integrated Heat Spreader (IHS) to spread out the heat generated from the die. See Section 1.1.1 for a complete terminology listing. The processor utilizes a PGA370 socket for installation into the motherboard.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Figure 23. Package Dimensions Table 35. Intel® Pentium® III Processor Package Dimensions Millimeters Inches Symbol Minimum Maximum A1 0.787 A2 1.000 B1 B2 Notes Minimum Maximum 0.889 0.031d 0.035 1.200 0.039 0.047 11.226 11.329 0.442 0.446 9.296 9.398 0.366 0.370 C1 23.495 max 0.925 max C2 21.590 max 0.850 max D 49.428 49.632 1.946 1.954 D1 45.466 45.974 1.790 1.810 G1 0.000 17.780 0 0.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz The bare processor die has mechanical load limits that should not be exceeded during heat sink assembly, mechanical stress testing, or standard drop and shipping conditions. The heatsink attach solution must not induce permanent stress into the processor substrate with the exception of a uniform load to maintain the heatsink to the processor thermal interface. The package dynamic and static loading parameters are listed in Table 36.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 5.1.1 FC-PGA2 Mechanical Specifications The following figure is provided to aid in the design of heatsink and clip solutions. Also, it is used to demonstrate where pin-side capacitors will be located on the processor. Table 31 includes the measurements for these dimensions in both inches and millimeters. Figure 24. Package Dimensions for FC-PGA2 Table 37.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 37. Package Dimensions for Intel® Pentium® III Processor FC-PGA2 Package Millimeters Inches Symbol Minimum Pin TP Maximum Notes Minimum 0.508 Diametric True Position (Pin-to-Pin) Maximum Notes 0.020 Diametric True Position (Pin-to-Pin) NOTE: Capacitors will be placed on the pin-side of the FC-PGA package in the area defined by G1, G2, and G3. This area is a keepout zone for motherboard designers.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 5.2 Processor Markings The following figure exemplifies the processor top-side markings and it is provided to aid in the identification of an Pentium III processor for the PGA370 socket. Table 35 and Table 37 list the measurements for the package dimensions. Figure 26.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Figure 28. Top Side Processor Markings for FC-PGA2 GRP1LN1 GRP1LN2 GRP2LN1 GRP2LN2 5.3 GRP1LN1: INTEL (m)(c) '01_-_{Country of Origin} GRP1LN2: {Core freq}/{Cache}/{Bus Freq}/{Voltage} GRP2LN1: {FPO}-{S/N} GRP2LN2: PENTIUM III {S-Spec} Recommended Mechanical Keep-Out Zones Figure 29. Volumetric Keep-Out for FC-PGA and FC-PGA2 1, 2 NOTES: 1. This drawing applies to FC-PGA2 package.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Figure 30. Component Keep-Out 5.4 Processor Signal Listing Table 39 and Table 40 provide the processor pin definitions. The signal locations on the PGA370 socket are to be used for signal routing, simulation, and component placement on the baseboard. Figure 31 provides a pin-side view of the Pentium III processor pinout.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Figure 31.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 39. Signal Listing in Order by Signal Name Pin No. AK8 Datasheet Pin Name A3# Signal Group Table 39. Signal Listing in Order by Signal Name (Continued) Pin No.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 39. Signal Listing in Order by Signal Name (Continued) Pin No. Datasheet Pin Name Signal Group Table 39. Signal Listing in Order by Signal Name (Continued) Pin No.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 39. Signal Listing in Order by Signal Name (Continued) Pin No. F36 Datasheet Pin Name GND Signal Group Table 39. Signal Listing in Order by Signal Name (Continued) Pin No.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 39. Signal Listing in Order by Signal Name (Continued) Pin No. AK30 AM2 Datasheet 6 Pin Name Signal Group Table 39. Signal Listing in Order by Signal Name (Continued) Pin No.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 39. Signal Listing in Order by Signal Name (Continued) Pin No. Datasheet Pin Name Signal Group Table 39. Signal Listing in Order by Signal Name (Continued) Pin No.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 40. Signal Listing in Order by Pin Number Pin No. A3 Datasheet Pin Name D29# Signal Group AGTL+ I/O Table 40. Signal Listing in Order by Pin Number (Continued) Pin No. AD34 Pin Name GND Signal Group Power/Other 3 A5 D28# AGTL+ I/O AD36 VCC1.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 40. Signal Listing in Order by Pin Number (Continued) Pin No. Datasheet Pin Name Signal Group Table 40. Signal Listing in Order by Pin Number (Continued) Pin No.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 40. Signal Listing in Order by Pin Number (Continued) Pin No. Datasheet Pin Name Signal Group Table 40. Signal Listing in Order by Pin Number (Continued) Pin No.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 40. Signal Listing in Order by Pin Number (Continued) Pin No. E31 Datasheet Pin Name DEP4# Signal Group AGTL+ I/O Table 40. Signal Listing in Order by Pin Number (Continued) Pin No.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 40. Signal Listing in Order by Pin Number (Continued) Pin No. R34 Pin Name GND Signal Group Table 40. Signal Listing in Order by Pin Number (Continued) Pin No.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz NOTES: 1. These pins are required for backwards compatibility with other Intel processors. They are not used by the Pentium III processor. Refer to the appropriate platform design guide and Section 7.1 for implementation details. 2. RESET# signal must be connected to pins AH4 and X4 for backwards compatibility. Refer to the appropriate platform design guide and Section 7.1 for implementation details.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 6.0 Boxed Processor Specifications The Pentium III processor for the PGA370 socket is also offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from motherboards and standard components. The boxed Pentium III processor for the PGA370 socket will be supplied with an unattached fan heatsink.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz The fan heatsink is designed to allow visibility of the FC-PGA processor markings located on top of the package. The FC-PGA processor markings are visible after installation of the fan heatsink due to notched sides of the heatsink base (see Figure 34). The boxed processor fan heatsink is also asymmetrical in that the mechanical step feature (see Figure 33) must sit over the socket’s cam.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 6.1.2 Boxed Processor Heatsink Weight The boxed processor thermal cooling solution will not weigh more than 180 grams. Figure 34. Dimensions of Notches in Heatsink Base 6.1.3 Boxed Processor Thermal Cooling Solution Clip The boxed processor thermal solution requires installation by a system integrator to secure the thermal cooling solution to the processor after it is installed in the 370-pin socket ZIF socket.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz For the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Figure 36. Boxed Processor Fan Heatsink Power Cable Connector Description Pin Signal 1 GND Straight square pin, 3-pin terminal housing with polarizing ribs and friction locking ramp. 2 +12V 0.100" pin pitch, 0.025" square pin width. 3 SENSE Waldom/Molex P/N 22-01-3037 or equivalent. Match with straight pin, friction lock header on motherboard Waldom/Molex P/N 22-23-2031, AMP P/N 640456-3, or equivalent. 1 2 3 Table 41.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz 7.0 Processor Signal Description This section provides an alphabetical listing of all the Pentium III processor signals. The tables at the end of this section summarize the signals by direction: output, input, and I/O. 7.1 Alphabetical Signals Reference Table 42. Signal Description (Sheet 1 of 8) Name A[35:3]# Type I/O Description The A[35:3]# (Address) signals define a 236-byte physical memory address space.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 42. Signal Description (Sheet 2 of 8) Name Type Description The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor system bus agents, and must connect the appropriate pins of all such agents, if used. However, Pentium III processors do not observe assertions of the BERR# signal.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 42. Signal Description (Sheet 3 of 8) Name Type Description The BR0# and BR1# (Bus Request) pins drive the BREQ[1:0]# signals in the system. The BREQ[1:0]# signals are interconnected in a rotating manner to individual processor pins. The table below gives the rotating interconnect between the processor and bus signals.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 42. Signal Description (Sheet 4 of 8) Name Type Description The CPUPRES# signal is defined to allow a system design to detect the presence of a terminator device or processor in a PGA370 socket. Combined with the VID combination of VID[3:0]= 1111 (see Section 2.6), a system can determine if a socket is occupied, and whether a processor core is present.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 42. Signal Description (Sheet 5 of 8) Name Type Description When the FLUSH# input signal is asserted, processors write back all data in the Modified state from their internal caches and invalidate all internal cache lines. At the completion of this operation, the processor issues a Flush Acknowledge transaction. The processor does not cache any new data while the FLUSH# signal remains asserted.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 42. Signal Description (Sheet 6 of 8) Name Type Description I The PICCLK (APIC Clock) signal is an input clock to the processor and core logic or I/O APIC which is required for operation of all processors, core logic, and I/O APIC components on the APIC bus.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 42. Signal Description (Sheet 7 of 8) Name Description The RSP# (Response Parity) signal is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect the appropriate pins of all processor system bus agents. RSP# I RTTCTRL I The RTTCTRL input signal provides AGTL+ termination control.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 42. Signal Description (Sheet 8 of 8) Name 7.2 Type Description VID[3:0] O The VID[3:0] (Voltage ID) pins can be used to support automatic selection of power supply voltages. These pins are not signals, but are either an open circuit or a short circuit to VSS on the processor. The combination of opens and shorts defines the voltage required by the processor.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 44.
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz Table 45.