Intel® Celeron® M Processor Datasheet June 2004 Order Number: 300302-003
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Contents 1 Introduction ...................................................................................................................... 7 1.1 1.2 1.3 2 Low Power Features ...................................................................................................... 11 2.1 2.2 2.3 3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 Processor Pin-Out and Pin List ............................................................................ 37 Alphabetical Signals Reference .....................................
Figures 1 2 3 4 5 6 7 8 9 10 11 4 Clock Control States...................................................................................................................11 Illustration of Active State VCC Static and Ripple Tolerances ...................................................22 Illustration of Deep Sleep VCC Static and Ripple Tolerances ....................................................24 Micro-FCPGA Package Top and Bottom Isometric Views ........................................................
Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 23 24 25 26 27 28 References ................................................................................................................................9 Voltage Identification Definition ...............................................................................................17 FSB Pin Groups.......................................................................................................................19 Processor DC Absolute Maximum Ratings....
Revision History Revision -001 Order Number 300302 -002 300302 -003 300302 6 Description Date Initial release January 2004 • Added ULV 900 MHz and 1.40 GHz specs • Updated DINV[3:0]# and BPM3# pin direction • Added 1.
Introduction 1 Introduction The Intel® Celeron® M processor and the ultra low voltage (ULV) Intel® Celeron® M processor are high-performance, low-power mobile processors with several microarchitectural enhancements over existing mobile Intel Celeron processors. The Intel Celeron M processor is available at the following core frequencies in the Micro-FCBGA and Micro-FCPGA packaging technologies: • • • • 1.20 GHz (1.356 V) 1.30 GHz (1.356 V) 1.40 GHz (1.356 V) 1.50 GHz (1.
Introduction The new packed, double-precision, floating-point instructions enhance performance for applications that require greater range and precision, including scientific and engineering applications and advanced 3D geometry techniques, such as ray tracing. The processor’s 400-MHz FSB utilizes a split-transaction, deferred reply protocol.
Introduction 1.2 References The following documents may be beneficial when reading this document. Please note that “platform design guides,” when used throughout this document, refer to the following documents: • Intel852GM Chipset Platform Design Guide • Intel 855GM/855GME Chipset Platform Design Guide • Intel 855PM Chipset Platform Design Guide Table 1. References Order Number1 Document Intel 855PM Chipset Platform Design Guide http://developer.intel.
Introduction 10 Intel® Celeron® M Processor Datasheet
Low Power Features 2 Low Power Features 2.1 Clock Control and Low Power States The Intel Celeron M processor supports the AutoHALT, Stop Grant, Sleep, and Deep Sleep states for optimal power management. See Figure 1 for a visual representation of the processor lowpower states. Figure 1.
Low Power Features The system can generate a STPCLK# while the processor is in the AutoHALT Power-Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in AutoHALT Power-Down state, the processor will process bus snoops. 2.1.3 Stop-Grant State When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop-Grant Acknowledge special bus cycle.
Low Power Features the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is in the Stop Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation. Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will cause unpredictable behavior. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals.
Low Power Features • BPRI# control for address and control input buffers • Dynamic on-die termination disabling • Low VCCP (I/O termination voltage) The Intel Celeron M processor incorporates the DPWR# signal that controls the data bus input buffers on the processor. The DPWR# signal disables the buffers when not used and activates them only when data bus activity occurs, resulting in significant power savings with no performance impact.
Electrical Specifications 3 Electrical Specifications 3.1 FSB and GTLREF The Intel Celeron M processor FSB uses Advanced Gunning Transceiver Logic (AGTL+) signalling technology, a variant of GTL+ signalling technology with low power enhancements. This signalling technology provides improved noise margins and reduced ringing through lowvoltage swings and controlled edge rates. The termination voltage level for the Intel Celeron M processor AGTL+ signals is VCCP = 1.05 V (nominal).
Electrical Specifications 3.3.1 VCC Decoupling Regulator solutions need to provide bulk capacitance with a low effective series resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low-power states, must be provided by the voltage regulator solution. For more details on decoupling recommendations, please refer to the platform design guides.
Electrical Specifications Table 2. Voltage Identification Definition VID 3.5 5 4 3 2 1 0 VCC V 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.708 1.692 1.
Electrical Specifications 3.6 Signal Terminations and Unused Pins All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future Intel Celeron M processors. See Section 4.1 for a pin listing of the processor and the location of all RSVD pins. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level.
Electrical Specifications Table 3. FSB Pin Groups Signal Group Signals1 Type AGTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, DEFER#, DPWR#, PREQ#, RESET#, RS[2:0]#, TRDY# AGTL+ Common Clock I/O Synchronous to BCLK[1:0] ADS#, BNR#, BPM[3:0]#2, BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#2 Signals AGTL+ Source Synchronous I/O Synchronous to assoc.
Electrical Specifications 3.9 Maximum Ratings Table 4 lists the processor’s maximum environmental stress ratings. The processor should not receive a clock while subjected to these conditions. Functional operating parameters are listed in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.
Electrical Specifications Table 5. Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes Intel Celeron M processor VCC 1.356 1.356 1.356 1.356 1.20 GHz Core VCC 1.30 GHz Core VCC 1.40 GHz Core VCC 1.50 GHz Core VCC Ultra low voltage Intel Celeron M Processor 800 MHz Core Vcc 900 MHz Core Vcc V 1, 2 1.004 1.004 VCC,BOOT Default VCC Voltage for initial power up 1.14 1.20 1.26 V 2, 7 VCCP AGTL+ Termination Voltage 0.997 1.05 1.
Electrical Specifications Table 5. Voltage and Current Specifications Symbol Parameter Min Typ ICC Deep Sleep at: Max 1.356 V (1.20 GHz) 1.356 V (1.30 GHz) 1.356 V (1.40 GHz) 1.356 V (1.50 GHz) 12.9 12.3 11.7 11.1 1.004 V (800 MHz ULV) 1.004 V (900 MHz ULV) 3.2 3 dICC/DT VCC power supply current slew rate ICCA ICCP IDSLP Unit Notes A 4 0.5 A/ns 6, 8 ICC for VCCA supply 120 mA ICC for VCCP supply 2.5 A NOTES: 1. The typical values shown are the VID encoded voltages.
Electrical Specifications Table 6. Voltage Tolerances for Intel Celeron M Processor with VID = 1.356 V (Active State) VID = 1.356 V, Offset = 0% ACTIVE Mode STATIC VCC, A VCC, V 0 Ripple Min Max Min Max 1.356 1.336 1.376 1.326 1.386 0.8 1.354 1.333 1.374 1.323 1.384 1.6 1.351 1.331 1.372 1.321 1.382 2.3 1.349 1.329 1.369 1.319 1.379 3.1 1.347 1.326 1.367 1.316 1.377 3.9 1.344 1.324 1.365 1.314 1.375 4.7 1.342 1.322 1.362 1.312 1.372 5.4 1.340 1.319 1.
Electrical Specifications Table 7. Voltage Tolerances for Intel Celeron M Processor with VID = 1.356 V (Deep Sleep State) VID =1.356 V, Offset = 1.2% Mode Deep Sleep STATIC ICC, A VCC, V 0.0 0.8 Ripple Min Max Min Max 1.340 1.319 1.360 1.309 1.370 1.337 1.317 1.358 1.307 1.368 1.6 1.335 1.314 1.355 1.304 1.365 2.5 1.332 1.312 1.353 1.302 1.363 3.3 1.330 1.310 1.350 1.300 1.360 4.1 1.327 1.307 1.348 1.297 1.358 4.9 1.325 1.305 1.345 1.295 1.355 5.7 1.
Electrical Specifications Table 8. Voltage Tolerances for ULV Intel Celeron M Processor with VID = 1.004 V (Active State) VID = 1.004 V, Offset = 0% ACTIVE Mode STATIC VCC, A VCC, V Ripple Min Max Min Max 0 1.004 0.989 1.019 0.979 1.029 0.3 1.003 0.988 1.018 0.978 1.028 0.5 1.002 0.987 1.017 0.977 1.027 0.8 1.002 0.986 1.017 0.976 1.027 1.1 1.001 0.986 1.016 0.976 1.026 1.4 1.000 0.985 1.015 0.975 1.025 1.6 0.999 0.984 1.014 0.974 1.024 1.9 0.998 0.
Electrical Specifications Table 9. Voltage Tolerances for ULV Intel Celeron M Processor with VID = 1.004 V (Deep Sleep State) VID =1.004 V, Offset = 1.2% Deep Sleep Mode STATIC ICC, A VCC, V 0.0 0.2 Ripple Min Max Min Max 0.992 0.977 1.007 0.967 1.017 0.991 0.976 1.006 0.966 1.016 0.4 0.991 0.976 1.006 0.966 1.016 0.6 0.990 0.975 1.005 0.965 1.015 0.9 0.989 0.974 1.004 0.964 1.014 1.1 0.989 0.974 1.004 0.964 1.014 1.3 0.988 0.973 1.003 0.963 1.013 1.5 0.
Electrical Specifications Table 11. AGTL+ Signal Group DC Specifications Symbol VCCP Parameter Min I/O Voltage 0.997 GTLREF Reference Voltage 2/3 VCCP 2% VIH Input High Voltage VIL Input Low Voltage VOH Output High Voltage Typ Max Unit Notes1 1.05 1.102 V 2/3 VCCP 2/3 VCCP + 2% V 6 GTLREF+0.1 VCCP+0.1 V 3,4,6 -0.1 GTLREF-0.1 V 2 VCCP 4,6 Termination Resistance 47 55 63 RON Buffer On Resistance 17.7 24.7 32.
Electrical Specifications 5. Measured at 0.9 x VCCP. 6. For Vin between 0V and VCCP. Measured when the driver is tristated. 7. Cpad includes die capacitance only. No package parasitics are included. Table 13. Open Drain Signal Group DC Specifications Symbol Parameter Min Typ Max VCCP Unit Notes1 V 3 VOH Output High Voltage VOL Output Low Voltage 0 0.20 V IOL Output Low Current 16 50 mA 2 ILO Leakage Current ± 200 µA 4 Cpad Pad Capacitance 3.0 pF 5 1.7 2.3 NOTES: 1.
Package Mechanical Specifications and Pin Information 4 Package Mechanical Specifications and Pin Information The processor is available in 478-pin Micro-FCPGA and 479 ball Micro-FCBGA packages. Different views of the Micro-FCPGA package are shown in Figure 4 through Figure 6. Package dimensions are shown in Table 14. Different views of the Micro-FCBGA package are shown in Figure 8 through Figure 10. Package dimensions are shown in Table 15.
Package Mechanical Specifications and Pin Information Figure 5. Micro-FCPGA Package - Top and Side Views SUBSTRATE KEEPO UT ZO NE DO NOT CONTACT PACKAGE IN S ID E T H IS L IN E 7 (K 1) 8 places 5 (K) 4 places 0.286 A 1.25 M A X (A 3) D1 35 (D ) Ø 0.32 (B ) 478 places E1 35 (E) A2 P IN A 1 C OR N ER 2.03 ± 0.08 (A 1) NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 14 for details.
Package Mechanical Specifications and Pin Information Figure 6. Micro-FCPGA Package - Bottom View 14 (K3) AF AD AB Y V T P M K H F D B AE AC AA W U R 14 (K3 ) N L J G E C A 1 25X 1.27 (e) 3 2 5 4 7 6 9 8 13 11 10 12 15 14 17 16 19 18 21 20 23 22 25 24 26 2 5X 1.27 (e) NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 14 for details. Figure 7.
Package Mechanical Specifications and Pin Information Table 14. Micro-FCPGA Package Dimensions Symbol Parameter Min Max Unit A Overall height, top of die to package seating plane 1.88 2.02 mm - Overall height, top of die to PCB surface, including socket (Refer to Note 1) 4.74 5.16 mm A1 Pin length 1.95 2.11 mm A2 Die height A3 Pin-side capacitor height B 0.82 mm - 1.25 mm Pin diameter 0.28 0.36 mm D Package substrate length 34.9 35.1 mm E Package substrate width 34.
Package Mechanical Specifications and Pin Information Figure 8.
Package Mechanical Specifications and Pin Information Figure 9. Micro-FCBGA Package Top and Side Views SUBSTRATE KEEPOUT ZONE DO NOT CONTACT PACKAGE INSIDE THIS LINE 7 (K1) 8 places 5 (K) 4 places 0.20 A A2 D1 35 (D) Ø 0.78 (b) 479 places E1 35 (E) K2 PIN A1 CORNER NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 15 for details.
Package Mechanical Specifications and Pin Information Figure 10. Micro-FCBGA Package Bottom View 1.625 (S) 4 places AF AD AB Y V T P M K H F D B AE AC 1.625 (S) 4 places AA W U R N L J G E C A 1 25X 1.27 (e) 3 2 5 4 7 6 9 8 10 11 13 15 17 19 21 23 25 12 14 16 18 20 22 24 26 25X 1.27 (e) NOTE: All dimensions in millimeters. Values shown for reference only.
Package Mechanical Specifications and Pin Information Table 15. Micro-FCBGA Package Dimensions Symbol Parameter Min Max Unit A Overall height, as delivered (Refer to Note 1) 2.60 2.85 mm A2 Die height 0.82 mm b Ball diameter 0.78 mm D Package substrate length 34.9 35.1 mm E Package substrate width 34.9 35.1 mm D1 Die length 10.56 mm E1 Die width 7.84 mm F To Package Substrate Center 17.5 mm G Die Offset from Package Center 1.133 mm e Ball pitch 1.
Package Mechanical Specifications and Pin Information 4.1 Processor Pin-Out and Pin List Figure 11 on the next page shows the top view pinout of the Intel Celeron M processor. The pin list is arranged in two different formats, shown in Table 23 and Table 24.
Package Mechanical Specifications and Pin Information Figure 11.
Package Mechanical Specifications and Pin Information Table 23. Pin Listing by Pin Name Table 23.
Package Mechanical Specifications and Pin Information Table 23. Pin Listing by Pin Name Pin Number Signal Buffer Type Direction D[17]# G25 Source Synch Input/Output D[18]# L23 Source Synch D[19]# M26 D[20]# Table 23.
Package Mechanical Specifications and Pin Information Table 23. Pin Listing by Pin Name Pin Number Signal Buffer Type Direction DSTBP[3]# AE25 Source Synch Input/Output FERR# D3 Open Drain GTLREF AD26 HIT# Table 23.
Package Mechanical Specifications and Pin Information Table 23. Pin Listing by Pin Name Pin Number Signal Buffer Type VCC F18 Power/Other VCC F20 VCC Table 23.
Package Mechanical Specifications and Pin Information Table 23. Pin Listing by Pin Name Pin Number Signal Buffer Type VCCP D12 Power/Other VCCP D14 VCCP Table 23.
Package Mechanical Specifications and Pin Information Table 23. Pin Listing by Pin Name Pin Number Signal Buffer Type VSS D11 Power/Other VSS D13 VSS Table 23.
Package Mechanical Specifications and Pin Information Table 23. Pin Listing by Pin Name Pin Number Signal Buffer Type VSS P2 Power/Other VSS P5 VSS Table 23.
Package Mechanical Specifications and Pin Information Table 23. Pin Listing by Pin Name Pin Number Signal Buffer Type VSS AC21 Power/Other VSS AC24 VSS Table 23.
Package Mechanical Specifications and Pin Information Table 24. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type A25 D[1]# Source Synch A26 VSS Power/Other AA1 VSS Power/Other AA2 A[16]# Source Synch Direction Input/ Output Input/ Output Input/ Output Table 24.
Package Mechanical Specifications and Pin Information Table 24.
Package Mechanical Specifications and Pin Information Table 24. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type AE6 VSS Power/Other AE7 VCCSENSE Power/Other AE8 VSS AE9 Direction Table 24.
Package Mechanical Specifications and Pin Information Table 24.
Package Mechanical Specifications and Pin Information Table 24. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type D17 VSS Power/Other D18 VCC Power/Other D19 VSS Power/Other D20 VCC Power/Other D21 VSS D22 Direction Table 24.
Package Mechanical Specifications and Pin Information Table 24. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction Table 24.
Package Mechanical Specifications and Pin Information Table 24. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction L22 VSS Power/Other L23 D[18]# Source Synch Input/ Output L24 DSTBP[1]# Source Synch Input/ Output L25 VSS Power/Other L26 D[26]# Source Synch M1 VSS Power/Other M2 DBSY# Common Clock M3 TRDY# Common Clock M4 VSS M5 Table 24.
Package Mechanical Specifications and Pin Information Table 24. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction T1 REQ[4]# Source Synch Input/ Output T2 REQ[2]# Source Synch Input/ Output T3 VSS Power/Other Input/ Output Table 24.
Package Mechanical Specifications and Pin Information Table 24.
4.2 Alphabetical Signals Reference Table 25. Signal Description (Sheet 1 of 7) Name Type Description 32 Input/ Output A[31:3]# (Address) define a 2 -byte physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the Intel Celeron M processor FSB.
Table 25. Signal Description (Sheet 2 of 7) Name COMP[3:0] Type Analog Description COMP[3:0] must be terminated on the system board using precision (1% tolerance) resistors. Refer to the platform design guides for more details on implementation. D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the FSB agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer.
Table 25. Signal Description (Sheet 3 of 7) Name Type Description DPSLP# Input DPSLP# when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state. In order to return to the Sleep State, DPSLP# must be deasserted. DPSLP# is driven by the ICH4-M component and also connects to the MCH-M component of the Intel 855PM, Intel 855GM, or 852GM chipset.
Table 25. Signal Description (Sheet 4 of 7) Name HIT# HITM# IERR# IGNNE# INIT# ITP_CLK[1:0] LINT[1:0] LOCK# Type Input/ Output Input/ Output Description HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Either FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. Output IERR# (Internal Error) is asserted by a processor as the result of an internal error.
Table 25. Signal Description (Sheet 5 of 7) Name Description Output Probe Ready signal used by debug tools to determine processor debug readiness. Please refer to the ITP700 Debug Port Design Guide and the platform design guides for more implementation details. Input Probe Request signal used by debug tools to request debug operation of the processor. Please refer to the ITP700 Debug Port Design Guide and the platform design guides for more implementation details.
Table 25. Signal Description (Sheet 6 of 7) Name Type Description Input SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts.
Table 25. Signal Description (Sheet 7 of 7) Name Description TRDY# Input TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both FSB agents. TRST# Input TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset.
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations The Intel Celeron M processor requires a thermal solution to maintain temperatures within operating limits. A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions include active or passive heatsinks or heat exchangers attached to the processor exposed die.
Thermal Specifications and Design Considerations Table 26. Power Specifications for the Intel Celeron M Processor Symbol TDP Core Frequency & Voltage Thermal Design Power 1.20 GHz & 1.356 V 1.30 GHz & 1.356 V 1.40 GHz & 1.356 V 1.50 GHz & 1.356 V 24.5 24.5 24.5 24.5 ULV Intel Celeron Mprocessor 800 MHz and 1.004 V 900 MHz and 1.004 V Symbol PAH, PSGNT PSLP PDSLP TJ Parameter Notes W At 100 °C, Notes 1, 4 Unit Notes 7 7 Min Typ Max Auto Halt, Stop Grant Power at: 1.356 V (1.20 GHz) 1.
Thermal Specifications and Design Considerations 5.1 Thermal Specifications 5.1.1 Thermal Diode The Intel Celeron M processor incorporates two methods of monitoring die temperature, the Intel Thermal Monitor and the thermal diode. The Intel Thermal Monitor (detailed in Section 5.1) must be used to determine when the maximum specified processor junction temperature has been reached.
Thermal Specifications and Design Considerations IFW=Is x (e(qVD/nkT) -1) Where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin). 5. The series resistance, RT, is provided to allow for a more accurate measurement of the diode junction temperature.
Thermal Specifications and Design Considerations 12.5% increments. On-Demand mode can be used at the same time automatic mode is enabled, however, if the system tries to enable the TCC via On-Demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode will take precedence. An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point.
Thermal Specifications and Design Considerations 68 Intel® Celeron® M Processor Datasheet
Debug Tools Specifications 6 Debug Tools Specifications Please refer to the ITP700 Debug Port Design Guide and the platform design guides for information regarding debug tools specifications. 6.1 Logic Analyzer Interface (LAI) Intel is working with logic analyzer vendors to provide LAIs for use in debugging Intel Celeron M processor systems. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor.
