Datasheet

Datasheet, Volume 2 119
Processor Integrated I/O (IIO) Configuration Registers
3.4.4.12 LMMIOL.LIMIT—Local MMIOL Limit
3.4.4.13 LMMIOH.BASE—Local MMIOH Base
3.4.4.14 LMMIOH.LIMIT—Local MMIOH Limit
Register: LMMIOL.LIMIT
Device: 8
Function: 0
Offset: 10Eh
Bit Attr Default Description
15:8 RW 00h
Local MMIOL Limit Address
This field corresponds to A[31:24] of MMIOL limit. An inbound or outbound
memory address that satisfies ‘local MMIOL base[15:8] ≤ A[31:24] ≤ local
MMIOL limit[15:8]’ is treated as a local peer-to-peer transaction that does not
cross an Intel
QuickPath Interconnect link.
Setting LMMIOL.BASE greater than LMMIOL.LIMIT disables local MMIOL peer-
to-peer.
This register is programmed once at boot time and does not change after that.
7:0 RO 0h Reserved
Register: LMMIOH.BASE
Device: 8
Function: 0
Offset: 110h
Bit Attr Default Description
15:10 RW 00h
Local MMIOH Base Address
This field corresponds to A[31:26] of MMIOH base. An inbound or outbound
memory address that satisfies ‘local MMIOH base upper[31:0]::local MMIOH
base[15:10] ≤ A[63:26] ≤ local MMIOH limit upper[31:0]::local MMIOH
limit[15:10]’ is treated as a local peer-to-peer transaction that does not cross
an Intel
QuickPath Interconnect link.
Setting LMMIOH.BASEU::LMMIOH.BASE greater than
LMMIOH.LIMITU::LMMIOH.LIMIT disables local MMIOH peer-to-peer.
This register is programmed once at boot time and does not change after that.
9:0 RO 0h Reserved
Register: LMMIOH.LIMIT
Device: 8
Function: 0
Offset: 112h
Bit Attr Default Description
15:10 RW 00h
Local MMIOH Limit Address
This field corresponds to A[31:26] of MMIOH limit. An inbound or outbound
memory address that satisfies ‘local MMIOH base upper[31:0]::local MMIOH
base[15:10] ≤ A[63:26] ≤ local MMIOH limit upper[31:0]::local MMIOH
limit[15:10]’ is treated as local a peer-to-peer transactions that does not cross
an Intel
QuickPath Interconnect link.
Setting LMMIOH.BASEU::LMMIOH.BASE greater than
LMMIOH.LIMITU::LMMIOH.LIMIT disables local MMIOH peer-to-peer.
This register is programmed once at boot time and does not change after that.
9:0 RO 000h Reserved