Datasheet

Datasheet, Volume 2 33
Processor Integrated I/O (IIO) Configuration Registers
Table 3-4. Device 3,5 PCI Express* Registers Legacy Configuration Map
DID VID 00h 80h
PCISTS PCICMD 04h
84h
CCR RID 08h
88h
HDR PLAT CLSR 0Ch 8Ch
10h PEGCAP PEGNXTPTR PEGCAPID 90h
14h DEVCAP 94h
SUBBUS SECBUS PBUS 18h DEVSTS DEVCTRL 98h
SECSTS IOLIM IOBAS 1Ch LNKCAP 9Ch
MLIM MBAS 20h LNKSTS LNKCON A0h
PMLIMIT PMBASE 24h SLTCAP A4h
PMBASEU 28h SLTSTS SLTCON A8h
PMLIMITU 2Ch ROOTCAP ROOTCON ACh
30h ROOTSTS B0h
34h DEVCAP2 B4h
38h DEVCTRL2 B8h
BCTRL INTPIN INTLIN 3Ch
BCh
SNXTPTR SCAPID 40h LNKSTS2 LNKCON2 C0h
SID SVID 44h
C4h
48h C8h
4Ch CCh
50h D0h
54h D4h
58h D8h
5Ch DCh
MSICTRL MSINXTPTR MSICAPID 60h PMCAP E0h
MSIAR 64h PMCSR E4h
MSIDR 68h E8h
MSIMSK 6Ch
ECh
MSIPENDING 70h
F0h
74h F4h
78h F8h
7Ch FCh