Datasheet

Processor Integrated I/O (IIO) Configuration Registers

58 Datasheet, Volume 2

3.3.4.16 DEVCAP—PCI Express* Device Capabilities Register

The PCI Express Device Capabilities register identifies device specific information for

the device.

Device: 0 (DMI), 3,5 (PCIe)

Function: 0

Offset: 94h

Bit Attr Default Description

31:28 RV 0h Reserved

27:26 RO 0h

Captured Slot Power Limit Scale

Does not apply to root ports or integrated devices.

25:18 RO 00h

Captured Slot Power Limit Value

Does not apply to root ports or integrated devices.

17:16 RV 0h Reserved

15 RO 1

Role Based Error Reporting

Integrated I/O is PCI Express Base Specification compliant and supports

this feature.

14 RO 0

Power Indicator Present on Device

Does not apply to root ports or integrated devices.

13 RO 0

Attention Indicator Present

Does not apply to root ports or integrated devices.

12 RO 0

Attention Button Present

Does not apply to root ports or integrated devices.

11:9 RO 000 Reserved

8:6 RO 000 Reserved

5RO 1

Extended Tag Field Supported

Integrated I/O devices support 8-bit tag.

4:3 RO 0h Reserved

2:0 RO

Dev 0: 000b

Dev 3,5: 001b

Max Payload Size Supported

IIO supports 256B payloads on PCI Express ports and 128B on the DMI port

(Device 0).