Datasheet

Datasheet, Volume 2 69
Processor Integrated I/O (IIO) Configuration Registers
3.3.4.24 SLTCON—PCI Express* Slot Control Register
The Slot Control register identifies the PCI Express specific slot control parameters for
operations such as Power Management.
Register: SLTCON
Device: 0 (DMI), 3, 5 (PCIe)
Function: 0
Offset: A8h
Bit Attr Default Description
15:13 RV 0h Reserved
12 RWS 0
Data Link Layer State Changed Enable
When set to 1, this field enables software notification when Data Link Layer
Link Active field is changed
11 RW 0
Electromechanical Interlock Control
If an electromechanical lock is implemented, a write of 1b to this field causes
the state of the interlock to toggle. Write of 0b has no effect. This bit always
returns a 0 when read. If electromechanical lock is not implemented, then
either a write of 1 or 0 to this register has no effect.
10 RWS 1
Power Controller Control
If a power controller is implemented, when written, this bit sets the power
state of the slot per the defined encodings. Reads of this field must reflect
the value from the latest write.
0 = Power On
1 = Power Off
9:8 RW 3h
Power Indicator Control
If a Power Indicator is implemented, writes to this register set the Power
Indicator to the written state. Reads of this field must reflect the value from
the latest write.
00 = Reserved
01 = On
10 = Blink (Integrated I/O drives 1.5-Hz square wave for Chassis mounted
LEDs)
11 = Off
When this register is written, the event is signaled using the virtual pins of
the Integrated I/O over a dedicated SMBus port.
Integrated I/O does not generate the Power_Indicator_On/Off/Blink
messages on PCI Express when this field is written to by software.
7:6 RW 3h
Attention Indicator Control
If an Attention Indicator is implemented, writes to this register set the
Attention Indicator to the written state.
Reads of this field reflect the value from the latest write.
00 = Reserved
01 = On
10 = Blink (The Integrated I/O drives 1.5 Hz square wave)
11 = Off
When this register is written, the event is signaled using the virtual pins of
the Integrated I/O over a dedicated SMBus port.
Integrated I/O does not generated the Attention_Indicator_On/Off/Blink
messages on PCI Express* when this field is written to by software.
5:0 RV 00h Reserved