Datasheet

Processor Integrated I/O (IIO) Configuration Registers
76 Datasheet, Volume 2
3.3.4.31 LNKSTS2—PCI Express* Link Control Register 2
3.3.4.32 PMCAP—Power Management Capabilities Register
The PM Capabilities Register defines the capability ID, next pointer and other power
management related support. The following PM registers/capabilities are added for
software compliance. For Device 0 DMI, this register should be RO and zero.
Register: LNKSTS2
Device: 0 (DMI), 3, 5 (PCIe)
Function: 0
Offset: C2h
Bit Attr Default Description
15:1 RO 0 Reserved
0RO 0
Compliance De-Emphasis
Current de-emphasis level - when operating at Gen2 speed. This is unused in
Gen1 speed.
1b = 3.5 dB
0b = 6 dB
Register: PMCAP
Device: 0 (DMI), 3, 5 (PCIe)
Function: 0
Offset: E0h
Bit Attr Default Description
31:27 RO 11001
Power Management Event (PME) Support
Bits 31, 30, and 27 must be set to 1 for PCI-to-PCI bridge structures
representing ports on root complexes.
26 RO 0
D2 Support
Integrated I/O does not support power management state D2.
25 RO 0
D1 Support
Integrated I/O does not support power management state D1.
24:22 RO 0h Reserved
21 RO 0 Device Specific Initialization
20 RV 0 Reserved
19 RO 0
PME Clock
This field is hardwired to 0h as it does not apply to PCI Express.
18:16 RO 011
Version
This field is set to 3h (PM 1.2 compliant) as version number for all PCI Express
ports.
15:8 RO 00h
Next Capability Pointer
This is the last capability in the chain and hence set to 0.
7:0 RO 01h
Capability ID
Provides the PM capability ID assigned by PCI-SIG.