Datasheet

Processor Integrated I/O (IIO) Configuration Registers
84 Datasheet, Volume 2
3.3.6 DMI Root Complex Register Block
This block is mapped into memory space, using register DMIRCBAR [Dev0:F0, offset
50h].
Table 3-6. DMI RCRB Registers
DMIVCH 00h 80h
DMIVCCAP1 04h DMILCAP 84h
DMIVCCAP2 08h DMILSTS DMILCTRL 88h
DMIVCCTL 0Ch
8Ch
DMIVC0RCAP 10h
90h
DMIVC0RCTL 14h
94h
DMIVC0RSTS
18h 98h
DMIVC1RCAP 1Ch
9Ch
DMIVC1RCTL 20h
A0h
DMIVC1RSTS
24h A4h
28h A8h
2Ch ACh
30h B0h
34h B4h
38h B8h
3Ch BCh
40h C0h
44h C4h
48h C8h
4Ch CCh
50h D0h
54h D4h
58h D8h
5Ch DCh
60h E0h
64h E4h
68h E8h
6Ch ECh
70h F0h
74h F4h
78h F8h
7Ch FCh