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Document Number: 320835-002

Intel

Core™ i7 Processor Extreme

Edition and Intel

Core™ i7

Processor

Datasheet, Volume 2

November 2008

Summary of content (98 pages)

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Intel® Core™ i7 Processor Extreme Edition and Intel® Core™ i7 Processor Datasheet, Volume 2 November 2008 Document Number: 320835-002
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Contents 1 Introduction ............................................................................................................ 11 1.1 Terminology ..................................................................................................... 11 1.1.1 Processor Terminology .......................................................................... 11 1.2 References ....................................................................................................... 13 2 Register Description .
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2.9.2 2.10 4 TAD_INTERLEAVE_LIST_0, TAD_INTERLEAVE_LIST_1 TAD_INTERLEAVE_LIST_2, TAD_INTERLEAVE_LIST_3 TAD_INTERLEAVE_LIST_4, TAD_INTERLEAVE_LIST_5 TAD_INTERLEAVE_LIST_6, TAD_INTERLEAVE_LIST_7................................59 Integrated Memory Controller Channel Control Registers.........................................60 2.10.1 MC_CHANNEL_0_DIMM_RESET_CMD MC_CHANNEL_1_DIMM_RESET_CMD MC_CHANNEL_2_DIMM_RESET_CMD .......................................................60 2.10.
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2.10.19 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_RD......................................... 74 2.10.20 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_RD......................................... 75 2.10.21 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_WR MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_WR MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_WR ........................................ 75 2.10.
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2.11 2.12 6 2.10.39 Error Injection Implementation ...............................................................84 Integrated Memory Controller Channel Address Registers........................................85 2.11.1 MC_DOD_CH0_0, MC_DOD_CH0_1, MC_DOD_CH0_2 ................................85 2.11.2 MC_DOD_CH1_0, MC_DOD_CH1_1, MC_DOD_CH1_2 ................................86 2.11.3 MC_DOD_CH2_0, MC_DOD_CH2_1, MC_DOD_CH2_2 ................................87 2.11.
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2.13 2.14 Datasheet MC_RIR_WAY_CH2_6, MC_RIR_WAY_CH2_7 MC_RIR_WAY_CH2_8, MC_RIR_WAY_CH2_9 MC_RIR_WAY_CH2_10, MC_RIR_WAY_CH2_11 MC_RIR_WAY_CH2_12, MC_RIR_WAY_CH2_13 MC_RIR_WAY_CH2_14, MC_RIR_WAY_CH2_15 MC_RIR_WAY_CH2_16, MC_RIR_WAY_CH2_17 MC_RIR_WAY_CH2_18, MC_RIR_WAY_CH2_19 MC_RIR_WAY_CH2_20, MC_RIR_WAY_CH2_21 MC_RIR_WAY_CH2_22, MC_RIR_WAY_CH2_23 MC_RIR_WAY_CH2_24, MC_RIR_WAY_CH2_25 MC_RIR_WAY_CH2_26, MC_RIR_WAY_CH2_27 MC_RIR_WAY_CH2_28, MC_RIR_WAY_CH2_29 MC_RIR_WAY_CH2_30, MC_RIR_WAY_CH2_31 ............
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Tables 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 8 References........................................................................................................13 Functions Specifically Handled by the Processor .....................................................18 Device 0, Function 0: Generic Non-core Registers ..................................................19 Device 0, Function 1: System Address Decoder Registers .................................
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Revision History Revision Number Description Date -001 Initial release. November 2008 -002 Updated section 2.2 and Table 2.3.
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Datasheet
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Introduction 1 Introduction The Intel® Core™ i7 processor Extreme Edition and Intel® Core™ i7 processor are intended for high performance high-end desktop, Uni-processor (UP) server, and workstation systems. The processor implements key new technologies: • Integrated Memory Controller • Point-to-point link interface based on Intel® QuickPath Interconnect (Intel® QPI). Reference to this interface may sometimes be abbreviated with Intel QPI throughout this document.
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Introduction more detailed information. Refer to http://developer.intel.com/ for future reference on up to date nomenclatures. • Eye Definitions — The eye at any point along the data channel is defined to be the creation of overlapping of a large number of Unit Interval of the data signal and timing width measured with respect to the edges of a separate clock signal at any other point. Each differential signal pair by combining the D+ and D- signals produces a signal eye.
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Introduction • Unit Interval (UI) — Signaling convention that is binary and unidirectional. In this binary signaling, one bit is sent for every edge of the forwarded clock, whether it be a rising edge or a falling edge. If a number of edges are collected at instances t1, t2, tn,...., tk then the UI at instance “n” is defined as: UI 1.2 n =t n -t n-1 References Material and concepts available in the following documents may be beneficial when reading this document. Table 1-1.
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Introduction 14 Datasheet
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Register Description 2 Register Description The processor supports PCI configuration space accesses using the mechanism denoted as Configuration Mechanism in the PCI specification as defined in the PCI Local Bus Specification, Revision 2.3, as well as the PCI Express* enhanced configuration mechanism as specified in the PCI Express Base Specification, Revision 1.1. All the registers are organized by bus, device, function, etc. as defined in the PCI Express Base Specification, Revision 1.1.
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Register Description Term Description RSVD Reserved Bit. This bit is reserved for future expansion and must not be written. The PCI Local Bus Specification, Revision 2.2 requires that reserved bits must be preserved. Any software that modifies a register that contains a reserved bit is responsible for reading the register, modifying the desired bits, and writing back the result. Reserved Bits Some of the processor registers described in this section contain reserved bits.
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Register Description at DID of 2C22h. Device 4, Function 3 contains the thermal control registers for Integrated Memory Controller Channel 0 and resides at DID of 2C23h. • Device 5: Integrated Memory Controller Channel 1. Device 5, Function 0 contains the control registers for Integrated Memory Controller Channel 1 and resides at DID of 2C28h. Device 5, Function 1 contains the address registers for Integrated Memory Controller Channel 1 and resides at DID of 2C29h.
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Register Description 2.4 Detailed Configuration Space Maps Table 2-2.
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Register Description Table 2-3.
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Register Description Table 2-4.
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Register Description Table 2-5.
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Register Description Table 2-6.
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Register Description Table 2-7.
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Register Description Table 2-8.
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Register Description Table 2-9.
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Register Description Table 2-10.
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Register Description Table 2-11.
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Register Description Table 2-12.
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Register Description Table 2-13.
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Register Description Table 2-14.
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Register Description Table 2-15.
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Register Description Table 2-16.
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Register Description Table 2-17.
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Register Description Table 2-18.
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Register Description Table 2-19.
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Register Description 2.5 PCI Standard Registers These registers appear in every function for every device. Note: Reserved bit locations are not shown in the following register tables. 2.5.1 VID - Vendor Identification Register The VID Register contains the vendor identification number. This 16-bit register, combined with the Device Identification Register uniquely identifies the manufacturer of the function within the processor. Writes to this register have no effect. 2.5.
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Register Description 2.5.3 RID - Revision Identification Register This register contains the revision number of the processor. The Revision ID (RID) is a traditional 8-bit Read Only (RO) register located at offset 08h in the standard PCI header of every PCI/PCI Express compatible device and function.
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Register Description 2.5.5 HDR - Header Type Register This register identifies the header layout of the configuration space. Device: Function: Offset: 0 0-1 0Eh Device: Function: Offset: 2 0-1, 4-5 0Eh Device: Function: Offset: 3 0-2, 4 0Eh Device: Function: Offset: 4-6 0-3 0Eh Bit Type Reset Value 7 RO 1 Description Multi-function Device Selects whether this is a multi-function device, that may have alternative configuration layouts. This bit is hardwired to 1 for devices in the processor.
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Register Description 2.5.7 PCICMD - Command Register This register defines the PCI 3.0 compatible command register values applicable to PCI Express space. Device: Function: Offset: 0 0-1 04h Device: Function: Offset: 2 0-1, 4-5 04h Device: Function: Offset: 3 0-2, 4 04h Device: Function: Offset: 4-6 0-3 04h Bit Type Reset Value 15:11 RV 0 Description Reserved. (by PCI SIG) INTxDisable: Interrupt Disable Controls the ability of the PCI Express port to generate INTx messages.
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Register Description 2.5.8 PCISTS - PCI Status Register The PCI Status register is a 16-bit status register that reports the occurrence of various error events on this device's PCI interface. Device: Function: Offset: 0 0-1 06h Device: Function: Offset: 2 0-1, 4-5 06h Device: Function: Offset: 3 0-2, 4 06h Device: Function: Offset: 4-6 0-3 06h Bit Type Reset Value 15 RO 0 Description Detect Parity Error (DPE) The host bridge does not implement this bit and is hardwired to a 0.
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Register Description Device: Function: Offset: 0 0-1 06h Device: Function: Offset: 2 0-1, 4-5 06h Device: Function: Offset: 3 0-2, 4 06h Device: Function: Offset: 4-6 0-3 06h Bit Type Reset Value Description Capability List (CLIST) 4 RO TBD This bit is hardwired to 1 to indicate to the configuration software that this device/function implements a list of new capabilities.
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Register Description Device: Function: Offset: Access as Bit 0 1 40h a Dword Type Reset Value Description PAM3_LOENABLE. 0D0000h-0D3FFFh Attribute (LOENABLE). This field controls the steering of read and write cycles that address the BIOS area from 0D0000h to 0D3FFFh. 25:24 RW 0 00 = DRAM Disabled: All accesses are directed to ESI. 01 = Read Only: All reads are sent to DRAM. All writes are forwarded to ESI. 10 = Write Only: All writes are send to DRAM. Reads are serviced by ESI.
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Register Description 2.6.2 SAD_PAM456 Register for legacy device 0, function 0 94h-97h address space. Device: Function: Offset: Access as 0 1 44h a Dword Bit Type Reset Value 21:20 RW 0 Description PAM6_HIENABLE. 0EC000h-0EFFFFh Attribute (HIENABLE). This field controls the steering of read and write cycles that address the BIOS area from 0EC000h to 0EFFFFh. 00 = DRAM Disabled: All accesses are directed to ESI. 01 = Read Only: All reads are sent to DRAM. All writes are forwarded to ESI.
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Register Description 2.6.3 SAD_HEN Register for legacy Hole Enable. Device: Function: Offset: Access as 0 1 48h a Dword Bit Type Reset Value 7 RW 0 Description HEN: Hole Enable This field enables a memory hole in DRAM space. The DRAM that lies "behind" this space is not remapped. 0 = No Memory hole. 1 = Memory hole from 15 MB to 16 MB. 2.6.4 SAD_SMRAM Register for legacy 9Dh address space. Note both IOH and non-core have this now.
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Register Description 2.6.5 SAD_PCIEXBAR Global register for PCIEXBAR address space. Device: Function: Offset: Access as 0 1 50h a Qword Bit Type Reset Value 39:20 RW 0 Description ADDRESS. Base address of PCIEXBAR. Must be naturally aligned to size; low order bits are ignored. SIZE. Size of the PCIEXBAR address space. (MAX bus number). 000 = 256 MB. 001 = Reserved. 3:1 RW 0 010 = Reserved. 011 = Reserved. 100 = Reserved. 101 = Reserved. 110 = 64 MB. 111 = 128 MB. ENABLE. 0 2.6.
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Register Description Device: Function: Offset: Access as 0 1 80h, 84h, 88h, 8Ch, 90h, 94h, 98h, 9Ch a Dword LIMIT 19:6 RW DRAM rule top limit address. Must be strictly greater than previous rule, even if this rule is disabled, unless this rule and all following rules are disabled. Lower limit is the previous rule (or 0 if it is first rule). This field is compared against MA[39:26] in the memory address map. - MODE 2:1 RW DRAM rule interleave mode.
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Register Description 2.7 Intel QPI Link Registers 2.7.1 QPI_QPILCL_L0, QPI_QPILCL_L1 This register provides Intel QPI Link Control. Device: Function: Offset: Access as Bit 2 0, 4 48h a Dword Type Reset Value Description L1_MASTER 21 RW Indicates that this end of the link is the L1 master. This link transmitter bit is an L1 power state master and can initiate an L1 power state transition.
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Register Description Device: Function: Offset: Access as 3 0 48h a Dword CHANNEL0_ACTIVE 8 RW 0 When set, indicate MC channel 0 is active. This bit is controlled (set/reset) by software only. This bit is required to be set for any active channel when INIT_DONE is set by software. Channel 0 AND Channel 1 active must both be set for a lockstep or mirrored pair. INIT_DONE 7 WO 0 MC initialize complete signal.
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Register Description 2.8.2 MC_STATUS This register is the MC primary status register. Device: Function: Offset: Access as 3 0 4Ch a Dword Bit Type Reset Value 4 RO 1 Description ECC_ENABLED. ECC is enabled. CHANNEL2_DISABLED 2 RO 0 Channel 2 is disabled. This can be factory configured or if Init done is written without the channel_active being set. Clocks in the channel will be disabled when this bit is set. CHANNEL1_DISABLED 1 RO 0 0 RO 0 Channel 1 is disabled.
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Register Description 2.8.3 MC_SMI_SPARE_DIMM_ERROR_STATUS SMI sparing DIMM error threshold overflow status register. This bit is set when the perDIMM error counter exceeds the specified threshold. The bit is reset by BIOS. Device: Function: Offset: Access as 3 0 50h a Dword Bit Type 13:12 RW0C Reset Value Description 0 REDUNDANCY_LOSS_FAILING_DIMM 0 DIMM_ERROR_OVERFLOW_STATUS The ID for the failing DIMM when redundancy is lost. This 12-bit field is the per dimm error overflow status bits.
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Register Description 2.8.4 MC_SMI_SPARE_CNTRL System Management Interrupt and Spare control register. Device: Function: Offset: Access as Bit 16 3 0 54h a Dword Type RW Reset Value 0 Description INTERRUPT_SELECT_NMI 1 = Enable NMI signaling. 0 = Disable NMI signaling. If both NMI and SMI enable bits are set, then only SMI is sent. INTERRUPT_SELECT_SMI 1 = Enable SMI signaling. 0 = Disable SMI signaling. 15 RW 0 If both NMI and SMI enable bits are set, then only SMI is sent.
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Register Description 2.8.6 MC_CHANNEL_MAPPER Channel mapping register. The sequence of operations to update this register is: Read MC_Channel_Mapper register Compare data read to data to be written. If different, then write. Poll MC_Channel_Mapper register until the data read matches data written. Device: Function: Offset: Access as 3 0 60h a Dword Bit Type Reset Value Description RDLCH2. Mapping of Logical Channel 2 to physical channel for Reads.
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Register Description 2.8.7 MC_MAX_DOD This register defines the MAX number of DIMMS, RANKS, BANKS, ROWS, COLS among all DIMMS populating the three channels. The Memory Init logic uses this register to cycle through all the memory addresses writing all 0's to initialize all locations. This register is also used for scrubbing and sparing and must always be programmed if any DODs are programmed. Device: Function: Offset: Access as 3 0 64h a Dword Bit Type Reset Value Description MAXNUMCOL.
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Register Description 2.8.8 MC_RD_CRDT_INIT These registers contain the initial read credits available for issuing memory reads. TAD read credit counters are loaded with the corresponding values at reset and anytime this register is written. BIOS must initialize this register with appropriate values depending on the level of Isoch support in the platform.
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Register Description 2.8.9 MC_CRDT_WR_THLD This is the Memory Controller Write Credit Thresholds register. A Write threshold is defined as the number of credits reserved for this priority (or higher) request. It is required that High threshold be greater than or equal to Crit threshold, and that both be lower than the total Write Credit init value. BIOS must initialize this register with appropriate values depending on the level of Isoch support in the platform.
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Register Description 2.8.11 MC_SCRUBADDR_HI This register pair contains part of the address of the last patrol scrub request issued. When running memtest, the failing address is logged in this register on memtest errors. Software can write the next address into this register. Scrubbing must be disabled to reliably read and write this register. Device: Function: Offset: Access as 3 0 7Ch a Dword Bit Type Reset Value 9:8 RW 0 Description CHNL.
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Register Description 2.9 TAD – Target Address Decoder Registers 2.9.1 TAD_DRAM_RULE_0, TAD_DRAM_RULE_2, TAD_DRAM_RULE_4, TAD_DRAM_RULE_6, TAD_DRAM_RULE_1 TAD_DRAM_RULE_3 TAD_DRAM_RULE_5 TAD_DRAM_RULE_7 TAD DRAM rules. Address map for channel determination within a package. All addresses sent to this HOME agent must hit a valid enabled DRAM_RULE. No error will be generated if they do not hit a valid location and memory aliasing will happen.
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Register Description 2.9.2 TAD_INTERLEAVE_LIST_0, TAD_INTERLEAVE_LIST_2, TAD_INTERLEAVE_LIST_4, TAD_INTERLEAVE_LIST_6, TAD_INTERLEAVE_LIST_1 TAD_INTERLEAVE_LIST_3 TAD_INTERLEAVE_LIST_5 TAD_INTERLEAVE_LIST_7 TAD DRAM package assignments. When the corresponding DRAM_RULE hits, a 3-bit number (determined by mode) is used to index into the Interleave_List Branches to determine which channel the DRAM request belongs to.
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Register Description Device: Function: Offset: Access as 3 1 C0h, C4h, C8h, CCh, D0h, D4h, D8h, DCh a Dword Logical Channel2. Index 010 of the Interleave List. Bits determined from the matching TAD_DRAM_RULE mode. 9:8 RW - 00 = Logical channel 0 01 = Logical channel 1 10 = Logical channel 2 11 = Reserved Logical Channel1. Index 001 of the Interleave List. Bits determined from the matching TAD_DRAM_RULE mode.
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Register Description 2.10.2 MC_CHANNEL_0_DIMM_INIT_CMD MC_CHANNEL_1_DIMM_INIT_CMD MC_CHANNEL_2_DIMM_INIT_CMD Integrated Memory Controller DIMM initialization command register. This register is used to sequence the channel through the physical layer training required for DDR. Device: Function: Offset: Access as Bit 4, 5, 6 0 54h a Dword Type Reset Value Description ASSERT_CKE.
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Register Description 2.10.3 MC_CHANNEL_0_DIMM_INIT_PARAMS MC_CHANNEL_1_DIMM_INIT_PARAMS MC_CHANNEL_2_DIMM_INIT_PARAMS Initialization sequence parameters are stored in this register. Each field is 2^n count. Device: Function: Offset: Access as Bit 4, 5, 6 0 58h a Dword Type Reset Value Description DIS_3T. 26 RW 0 When set, 3T mode will not be enabled as a part of the MRS write to the RDIMM.
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Register Description 2.10.4 MC_CHANNEL_0_DIMM_INIT_STATUS MC_CHANNEL_1_DIMM_INIT_STATUS MC_CHANNEL_2_DIMM_INIT_STATUS The initialization state is stored in this register. This register is cleared on a new training command. Device: Function: Offset: Access as 4, 5, 6 0 5Ch a Dword Bit Type Reset Value 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 Description RCOMP_CMPLT. When set, indicates that RCOMP command has complete.
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Register Description 2.10.5 MC_CHANNEL_0_DDR3CMD MC_CHANNEL_1_DDR3CMD MC_CHANNEL_2_DDR3CMD DDR3 Configuration Command. This register is used to issue commands to the DIMMs such as MRS commands. The register is used by setting one of the *_VALID bits along with the appropriate address and destination RANK. The command is then issued directly to the DIMM. Care must be taken in using this register as there is no enforcement of timing parameters related to the action taken by a DDR3CMD write.
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Register Description 2.10.6 MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_2_REFRESH_THROTTLE_SUPPORT This register supports Self Refresh and Thermal Throttle functions. Device: Function: Offset: Access as 4, 5, 6 0 68h a Dword Bit Type Reset Value Description INC_ENTERPWRDWN_RATE. Powerdown rate will be increased during thermal throttling based on the following configurations.
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Register Description 2.10.8 MC_CHANNEL_0_MRS_VALUE_2 MC_CHANNEL_1_MRS_VALUE_2 MC_CHANNEL_2_MRS_VALUE_2 The initial MRS register values for MR2. This register also contains the values used for RC0 and RC2 writes for registered DIMMs. These values are used during the automated training sequence when MRS writes or registered DIMM RC writes are used. The RC fields do not need to be programmed if the address inversion and 3T/1T transitions are disabled.
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Register Description 2.10.10 MC_CHANNEL_0_RANK_TIMING_A MC_CHANNEL_1_RANK_TIMING_A MC_CHANNEL_2_RANK_TIMING_A This register contains parameters that specify the rank timing used. All parameters are in DCLK. Device: Function: Offset: Access as Bit 4, 5, 6 0 80h a Dword Type Reset Value Description tddWrTRd. Minimum delay between a write followed by a read to different DIMMs. 000 = 1 001 = 2 28:26 RW 0 010 = 3 011 = 4 100 = 5 101 = 6 110 = 7 111 = 8 tdrWrTRd.
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Register Description Device: Function: Offset: Access as 4, 5, 6 0 80h a Dword tddRdTWr. Minimum delay between Read followed by a Write to different DIMMs. 0000 = 2 0001 = 3 0010 = 4 0011 = 5 0100 = 6 18:15 RW 0 0101 = 7 0110 = 8 0111 = 9 1000 = 10 1001 = 11 1010 = 12 1011 = 13 1100 = 14 tdrRdTWr. Minimum delay between Read followed by a write to different ranks on the same DIMM.
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Register Description Device: Function: Offset: Access as 4, 5, 6 0 80h a Dword tddRdTRd. Minimum delay between reads to different DIMMs. 000 = 2 001 = 3 6:4 RW 0 010 = 4 011 = 5 100 = 6 101 = 7 110 = 8 111 = 9 tdrRdTRd. Minimum delay between reads to different ranks on the same DIMM. 000 = 2 001 = 3 3:1 RW 0 010 = 4 011 = 5 100 = 6 101 = 7 110 = 8 111 = 9 tsrRdTRd. 0 RW 0 Minimum delay between reads to the same rank.
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Register Description 2.10.11 MC_CHANNEL_0_RANK_TIMING_B MC_CHANNEL_1_RANK_TIMING_B MC_CHANNEL_2_RANK_TIMING_B This register contains parameters that specify the rank timing used. All parameters are in DCLK. Device: Function: Offset: Access as Bit 4, 5, 6 0 84h a Dword Type Reset Value Description B2B_CAS_DELAY. 20:16 RW 0 Controls the delay between CAS commands in DCLKS. The minimum spacing is 4 DCLKS. Values below 3 have no effect. A value of 0 disables the logic.
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Register Description 2.10.12 MC_CHANNEL_0_BANK_TIMING MC_CHANNEL_1_BANK_TIMING MC_CHANNEL_2_BANK_TIMING This register contains parameters that specify the bank timing parameters. These values are in DCLK. The values in these registers are encoded where noted. All of these values apply to commands to the same rank only. Device: Function: Offset: Access as 2.10.13 4, 5, 6 0 88h a Dword Bit Type Reset Value 21:17 RW 0 tWTPr. Minimum Write CAS to Precharge command delay.
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Register Description 2.10.14 MC_CHANNEL_0_CKE_TIMING MC_CHANNEL_1_CKE_TIMING MC_CHANNEL_2_CKE_TIMING This register contains parameters that specify the CKE timings. All units are in DCLK. Device: Function: Offset: Access as Bit 4, 5, 6 0 90h a Dword Reset Value Type Description tRANKIDLE. 31:24 RW 0 23:21 RW 0 20:11 RW 0 10:3 RW 0 2:0 RW 0 Rank will go into powerdown after it has been idle for the specified number of dclks. tRANKIDLE covers max(txxxPDEN). Minimum value is tWRAPDEN.
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Register Description 2.10.16 MC_CHANNEL_0_RCOMP_PARAMS MC_CHANNEL_1_RCOMP_PARAMS MC_CHANNEL_2_RCOMP_PARAMS This register contains parameters that specify Rcomp timings. Device: Function: Offset: Access as 4, 5, 6 0 98h a Dword Bit Type Reset Value 16 RW 1 15:10 RW 2 Description RCOMP_EN. Enable Rcomp. When set, the Integrated Memory Controller will do the programmed blocking of requests and send indications. RCOMP_CMD_DCLK.
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Register Description 2.10.18 MC_CHANNEL_0_ODT_PARAMS2 MC_CHANNEL_1_ODT_PARAMS2 MC_CHANNEL_2_ODT_PARAMS2 This register contains parameters that specify Forcing ODT on Specific ranks. This register is used in debug only and not during normal operation. Device: Function: Offset: Access as 2.10.19 4, 5, 6 0 A0h a Dword Bit Type Reset Value 9 RW 0 MCODT_Writes. Drive MC ODT on reads and writes. 8 RW 0 FORCE_MCODT. Force MC ODT to always be asserted. 7 RW 0 FORCE_ODT7.
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Register Description 2.10.20 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_RD This register contains the ODT activation matrix for RANKS 4 to 7 for Reads. Device: 4, 5, 6 Function:)0 Offset: A8h Access as a Dword 2.10.21 Bit Type Reset Value 31:24 RW 1 ODT_RD7. Bit patterns driven out onto ODT pins when Rank7 is read. 23:16 RW 1 ODT_RD6. Bit patterns driven out onto ODT pins when Rank6 is read. Description 15:8 RW 4 ODT_RD5.
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Register Description 2.10.23 MC_CHANNEL_0_WAQ_PARAMS MC_CHANNEL_1_WAQ_PARAMS MC_CHANNEL_2_WAQ_PARAMS This register contains parameters that specify settings for the Write Address Queue. Device: Function: Offset: Access as 4, 5, 6 0 B4h a Dword Bit Type Reset Value 29:25 RW 6 24:20 RW 31 Description PRECASWRTHRESHOLD. Threshold above which Medium-Low Priority reads cannot PRE-CAS write requests. PARTWRTHRESHOLD. Threshold used to raise the priority of underfill requests in the scheduler.
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Register Description 2.10.24 MC_CHANNEL_0_SCHEDULER_PARAMS MC_CHANNEL_1_SCHEDULER_PARAMS MC_CHANNEL_2_SCHEDULER_PARAMS These are the parameters used to control parameters within the scheduler. Device: Function: Offset: Access as 4, 5, 6 0 B8h a Dword Bit Type Reset Value 12 RW 1 11 RW 0 10:6 RW 7 5 RW 0 3 RW 0 2:0 RW 0 Description CS_FOR_CKE_TRANSITION. Specifies if chip select is to be asserted when CKE transitions with PowerDown entry/exit and SelfRefresh exit. FLOAT_EN. 2.10.
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Register Description 2.10.26 MC_CHANNEL_0_TX_BG_SETTINGS MC_CHANNEL_1_TX_BG_SETTINGS MC_CHANNEL_2_TX_BG_SETTINGS These are the parameters used to set the Start Scheduler for TX clock crossing. This is used to send commands to the DIMMs.
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Register Description 2.10.28 MC_CHANNEL_0_EW_BGF_SETTINGS MC_CHANNEL_1_EW_BGF_SETTINGS MC_CHANNEL_2_EW_BGF_SETTINGS These are the parameters used to set the early warning RX clock crossing BGF. Device: Function: Offset: Access as 2.10.29 4, 5, 6 0 CCh a Dword Bit Type Reset Value 15:8 RW 1 Description ALIENRATIO. Dclk to Bclk ratio. Early warning Alien Ratio setting.
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Register Description 2.10.31 MC_CHANNEL_0_PAGETABLE_PARAMS1 MC_CHANNEL_1_PAGETABLE_PARAMS1 MC_CHANNEL_2_PAGETABLE_PARAMS1 These are the parameters used to control parameters for page closing policies.. Device: Function: Offset: Access as 4, 5, 6 0 D8h a Dword Bit Type Reset Value 15:8 RW 0 Description REQUESTCOUNTER. This field is the upper 8 MSBs of a 12-bit counter. This counter determines the window over which the page close policy is evaluated. 7:0 RW 0 ADAPTIVETIMEOUTCOUNTER.
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Register Description 2.10.33 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH0 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH1 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH2 Channel Bubble Generator ratios for CMD and DATA. Device: Function: Offset: Access as Bit 2.10.34 4, 5, 6 0 E0h a Dword Type Reset Value Description 15:8 RW 1 ALIENRATIO. DCLK to BCLK ratio. 7:0 RW 4 NATIVERATIO. UCLK to BCLK ratio.
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Register Description 2.10.36 MC_CHANNEL_0_ADDR_MATCH MC_CHANNEL_1_ADDR_MATCH MC_CHANNEL_2_ADDR_MATCH This register specifies the intended address or address range where ECC errors will be injected. It can be set to match memory address on a per channel basis. The address fields can be masked in the Mask bits. Any mask bits set to 1 will always match. To match all addresses, all of the mask bits can be set to 1.
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Register Description 2.10.37 MC_CHANNEL_0_ECC_ERROR_MASK MC_CHANNEL_1_ECC_ERROR_MASK MC_CHANNEL_2_ECC_ERROR_MASK This register contains mask bits for the memory controller and specifies at which ECC bit(s) the error injection should occur. Any bits set to a 1 will flip the corresponding ECC bit. Correctable errors can be injected by flipping 1 bit or the bits within a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or 23:16 and 31:24).
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Register Description 2.10.39 Error Injection Implementation The usage model is to program the MC_CHANNEL_X_ADDR_MATCH and MC_CHANNEL_X_ECC_ERROR_MASK registers before writing the command in MC_CHANNEL_X_ECC_ERROR_INJECT register. When writing the MC_CHANNEL_X_ECC_ERROR_INJECT register, the REPEAT_EN and MASK_HALF_CACHELINE bits need to be set to the desired values. To turn off the feature, write 0 to the MC_CHANNEL_X_ECC_ERROR_INJECT register.
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Register Description 2.11 Integrated Memory Controller Channel Address Registers 2.11.1 MC_DOD_CH0_0, MC_DOD_CH0_1, MC_DOD_CH0_2 Channel 0 DIMM Organization Descriptor Register. Device: Function: Offset: Access as Bit 4 1 48h, 4Ch, 50h a Dword Type Reset Value Description RANKOFFSET. 12:10 RW 0 9 RW 0 Rank Offset for calculating RANK. This corresponds to the first logical rank on the DIMM. The rank offset is always programmed to 0 for the DIMM 0 DOD registers. (DIMM 0 rank offset is always 0.
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Register Description 2.11.2 MC_DOD_CH1_0, MC_DOD_CH1_1, MC_DOD_CH1_2 Channel 1 DIMM Organization Descriptor Register. Device: Function: Offset: Access as Bit 5 1 48h, 4Ch, 50h a Dword Type Reset Value Description RANKOFFSET. Rank Offset for calculating RANK. 12:10 RW 0 9 RW 0 This field corresponds to the first logical rank on the DIMM. The rank offset is always programmed to 0 for the DIMM 0 DOD registers. (DIMM 0 rank offset is always 0.
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Register Description 2.11.3 MC_DOD_CH2_0, MC_DOD_CH2_1, MC_DOD_CH2_2 Channel 2 DIMM Organization Descriptor Register. Device: Function: Offset: Access as 6 1 48h, 4Ch, 50h a Dword Bit Type Reset Value 12:10 RW 0 Description RANKOFFSET. Rank Offset for calculating RANK. This field corresponds to the first logical rank on the DIMM. The rank offset is always programmed to 0 for the DIMM 0 DOD registers. (DIMM 0 rank offset is always 0.
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Register Description 2.11.4 MC_SAG_CH0_0, MC_SAG_CH0_3, MC_SAG_CH0_6, MC_SAG_CH1_1, MC_SAG_CH1_4, MC_SAG_CH1_7, MC_SAG_CH2_2, MC_SAG_CH2_5, MC_SAG_CH0_1, MC_SAG_CH0_4, MC_SAG_CH0_7, MC_SAG_CH1_2, MC_SAG_CH1_5, MC_SAG_CH2_0, MC_SAG_CH2_3, MC_SAG_CH2_6, MC_SAG_CH0_2 MC_SAG_CH0_5 MC_SAG_CH1_0 MC_SAG_CH1_3 MC_SAG_CH1_6 MC_SAG_CH2_1 MC_SAG_CH2_4 MC_SAG_CH2_7 Channel Segment Address Registers.
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Register Description 2.12 Integrated Memory Controller Channel Rank Registers 2.12.
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Register Description 2.12.
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Register Description 2.12.
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Register Description 2.12.
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Register Description 2.13 Memory Thermal Control 2.13.1 MC_THERMAL_CONTROL0 MC_THERMAL_CONTROL1 MC_THERMAL_CONTROL2 Controls for the Integrated Memory Controller thermal throttle logic for each channel. Device: Function: Offset: Access as 4, 5, 6 3 48h a Dword Bit Type Reset Value 2 RW 1 Description APPLY_SAFE. Enable the application of safe values while MC_THERMAL_PARAMS_B.SAFE_INTERVAL is exceeded. THROTTLE_MODE. S elects throttling mode.
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Register Description 2.13.3 MC_THERMAL_DEFEATURE0 MC_THERMAL_DEFEATURE1 MC_THERMAL_DEFEATURE2 Thermal Throttle defeature register for each channel. Device: Function: Offset: Access as 4, 5, 6 3 50h a Dword Bit Type Reset Value 0 RW1S 0 Description THERM_REG_LOCK. 2.13.4 When set, no further modification of all thermal throttle registers are allowed. This bit must be set to the same value for all channels.
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Register Description 2.13.5 MC_THERMAL_PARAMS_B0 MC_THERMAL_PARAMS_B1 MC_THERMAL_PARAMS_B2 Parameters used by the thermal throttling logic. Device: Function: Offset: Access as Bit 4, 5, 6 3 64h a Dword Type Reset Value Description SAFE_INTERVAL. 31:26 RW 1 25:16 RW 255 15:8 RW 1 7:0 RW 0 Safe values for cooling coefficient and duty cycle will be applied while the SAFE_INTERVAL is exceeded.
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Register Description 2.13.7 MC_CLOSED_LOOP0 MC_CLOSED_LOOP1 MC_CLOSED_LOOP2 This register controls the closed loop thermal response of the DRAM thermal throttle logic. It supports immediate thermal throttle and 2X refresh. In addition, the register is used to configure the throttling duty cycle. Device: Function: Offset: Access as Bit 4, 5, 6 3 84h a Dword Type Reset Value Description MIN_THROTTLE_DUTY_CYC.
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Register Description 2.13.9 MC_RANK_VIRTUAL_TEMP0 MC_RANK_VIRTUAL_TEMP1 MC_RANK_VIRTUAL_TEMP2 This register contains the 8 most significant bits [37:30] of the virtual temperature of each rank. The difference between the virtual temperature and the sensor temperature can be used to determine how fast fan speed should be increased. The value stored is right shifted one bit to the right with respect to the corresponding MC_Throttle_Offset register value.
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Register Description 2.13.11 MC_DDR_THERM_STATUS0 MC_DDR_THERM_STATUS1 MC_DDR_THERM_STATUS2 This register contains the status portion of the DDR_THERM# functionality as described in the processor datasheet (i.e., what is happening or has happened with respect to the pin). Device: Function: Offset: Access as 4, 5, 6 3 A4h a Dword Bit Type Reset Value 2 RO 0 1 RO 0 Description ASSERTION. An assertion edge was seen on DDR_THERM#. Write-1-to-clear. DEASSERTION.
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Register Description 2.14.2 MC_DIMM_CLK_RATIO This register is for the Requested DIMM clock ratio (Qclk). This is the data rate going to the DIMM. The clock sent to the DIMM is 1/2 of QCLK rate. Device: Function: Offset: Access as 3 4 54h a Dword Bit Type Reset Value 4:0 RW 6 Description QCLK_RATIO. Requested ratio of Qclk/Bclk.