Datasheet

Power Management
34 Intel® Xeon® Processor 3400 Series Datasheet, Volume 1
4.1.4 PCI Express* Link States
4.1.5 Interface State Combinations
4.2 Processor Core Power Management
While executing code, Enhanced Intel SpeedStep Technology optimizes the processor’s
frequency and core voltage based on workload. Each frequency and voltage operating
point is defined by ACPI as a P-state. When the processor is not executing code, it is
idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power C-
states have longer entry and exit latencies.
State Description
L0 Full on – Active transfer state.
L0s First Active Power Management low power state – Low exit latency.
L1 Lowest Active Power Management - Longer exit latency.
L3 Lowest power state (power-off) – Longest exit latency.
Table 4-2. G, S, and C State Combinations
Global (G)
State
Sleep
(S) State
Processor
Core
(C) State
Processor
State
System Clocks Description
G0 S0 C0 Full On On Full On
G0 S0 C1/C1E Auto-Halt On Auto-Halt
G0 S0 C3 Deep Sleep On Deep Sleep
G0 S0 C6
Deep Power
Down
On Deep Power Down
G1 — Power off Power off Off, except RTC Suspend to RAM
G1 S4 Power off Power off Off, except RTC Suspend to Disk
G2 S5 Power off Power off Off, except RTC Soft Off
G3 NA Power off Power off Power off Hard off