Datasheet

Power Management

36 Intel® Xeon® Processor 3400 Series Datasheet, Volume 1

Entry and exit of the C-States at the thread and core level are shown in Figure 4-2.

While individual threads can request low power C-states, power saving actions only

take place once the core C-state is resolved. Core C-states are automatically resolved

by the processor. For thread and core C-states, a transition to and from C0 is required

before entering any other C-state.

Note:

1. If enabled, the core C-state will be C1E if all active cores have also resolved to a core C1 state or higher.

Figure 4-2. Thread and Core C-State Entry and Exit

C1 C1E C6C3

MWAIT(C1), HLT

MWAIT(C6),

P_LVL3 I/O Read

MWAIT(C3),

P_LVL2 I/O Read

MWAIT(C1), HLT

(C1E Enabled)

Table 4-3. Coordination of Thread Power States at the Core Level

Processor Core

C-State

Thread 1

C0 C1 C3 C6

Thread 0

C0 C0 C0 C0

C0 C1

C3 C3

C0 C1

C3 C6