Datasheet

Intel® Xeon® Processor 3400 Series Datasheet, Volume 1 5
7 Electrical Specifications...........................................................................................59
7.1 Power and Ground Lands....................................................................................59
7.2 Decoupling Guidelines........................................................................................59
7.2.1 Voltage Rail Decoupling...........................................................................59
7.3 Processor Clocking (BCLK[0], BCLK#[0])..............................................................60
7.3.1 PLL Power Supply...................................................................................60
7.4 VCC Voltage Identification (VID)..........................................................................60
7.5 Reserved or Unused Signals................................................................................64
7.6 Signal Groups...................................................................................................64
7.7 Test Access Port (TAP) Connection.......................................................................67
7.8 Absolute Maximum and Minimum Ratings .............................................................67
7.9 DC Specifications ..............................................................................................68
7.9.1 Voltage and Current Specifications............................................................68
7.10 Platform Environmental Control Interface (PECI) DC Specifications...........................74
7.10.1 DC Characteristics..................................................................................75
7.10.2 Input Device Hysteresis ..........................................................................75
8 Processor Land and Signal Information ...................................................................77
8.1 Processor Land Assignments...............................................................................77
Figures
1-1 Intel
®
Xeon
®
Processor 3400 Series Platform Diagram ................................................. 10
2-1 Intel® Flex Memory Technology Operation..................................................................21
2-2 Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes ..................22
2-3 PCI Express Layering Diagram ...................................................................................24
2-4 Packet Flow through the Layers .................................................................................25
2-5 PCI Express* Related Register Structures in Processor .................................................26
4-1 Idle Power Management Breakdown of the Processor Cores ...........................................35
4-2 Thread and Core C-State Entry and Exit......................................................................36
4-3 Package C-State Entry and Exit..................................................................................40
7-1 VCC Static and Transient Tolerance Loadlines .............................................................71
7-2 Input Device Hysteresis ............................................................................................75
8-1 Socket Pinmap (Top View, Upper-Left Quadrant)..........................................................78
8-2 Socket Pinmap (Top View, Upper-Right Quadrant)........................................................79
8-3 Socket Pinmap (Top View, Lower-Left Quadrant)..........................................................80
8-4 Socket Pinmap (Top View, Lower-Right Quadrant)........................................................81