Datasheet

Signal Description
50 Intel® Xeon® Processor 3400 Series Datasheet, Volume 1
6.2 Memory Reference and Compensation
6.3 Reset and Miscellaneous Signals
Table 6-4. Memory Reference and Compensation
Signal Name Description Direction Type
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
Channel A and B Output DDR3 DIMM DQ Reference Voltage.
OAnalog
SM_RCOMP[2:0] System Memory Impedance Compensation. I Analog
Table 6-5. Reset and Miscellaneous Signals (Sheet 1 of 2)
Signal Name Description Direction Type
CFG[17:0]
Configuration signals:
The CFG signals have a default value of 1 if not
terminated on the board.
• CFG[1:0]: PCI Express Bifurcation
Intel Xeon
®
processor 3400 series:
11 = 1 x16 PCI Express
10 = 2 x8 PCI Express
01 = 4 x4 PCI Express (requires Intel 3420 or
3400 Chipset)
00 = Reserved
• CFG[2]: Reserved configuration land. A test point
may be placed on the board for this land.
• CFG[3]: Reserved configuration land.
• CFG[6:4]: Reserved configuration lands. A test
point may be placed on the board for this land.
• CFG[17:7]: Reserved configuration lands. Intel
does not recommend a test point on the board for
this land.
ICMOS
COMP0 Impedance compensation must be terminated on the
system board using a precision resistor. Refer to
Table 7-9 for the termination requirement.
IAnalog
COMP1
Impedance compensation must be terminated on the
system board using a precision resistor. Refer to
Table 7-9 for the termination requirement.
IAnalog
COMP2
Impedance compensation must be terminated on the
system board using a precision resistor. Refer to
Table 7-9 for the termination requirement.
IAnalog
COMP3
Impedance compensation must be terminated on the
system board using a precision resistor. Refer to
Table 7-9 for the termination requirement.
IAnalog
FC_x
Future Compatibility (FC) signals are signals that are
available for compatibility with other processors. A test
point may be placed on the board for these lands.
PM_EXT_TS#[1:0]
External Thermal Sensor Input: If the system
temperature reaches a dangerously high value then this
signal can be used to trigger the start of system
memory throttling.
ICMOS
PM_SYNC
Power Management Sync: A sideband signal to
communicate power management status from the
platform to the processor.
ICMOS
RESET_OBS#
This signal is an indication of the processor being reset.
O
Asynch
CMOS